DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 08/24/2023. It is noted, however, that applicant has not filed a certified copy of the KR10-2023-0111312 application as required by 37 CFR 1.55.
An attempt by the Office to electronically retrieve the priority document failed, see the notice of 01/24/2025 on file.
Election/Restrictions
Applicant’s election without traverse of Species I, Figures 4, 5, 7, and 8, in the reply filed on 07/19/2026 is acknowledged. Applicant asserted claims 1-19 read on the elected species. However, claims 13-19 are not drawn to the elected invention.
Claim 13 requires “second page buffer contacts in the connection region of the first memory cell array, electrically connected to a portion of the first page buffers of the first peripheral circuit, and electrically isolated from the first bit lines.” This is a feature of non-elected Species II, see items 1PCT and 3PCT in Figure 9 and paragraph 120 of the specification. The elected Species I differs from Species II in that Species I includes only a single group of page buffer contacts shared by the first memory cell array and the second memory cell array, see item PCT in Figure 5.
Claim 14 depends on claim 13 and includes additional details drawn to the embodiment of Figures 9 and 10 and therefore is also drawn to non-elected Species II.
Claim 15 requires “a second peripheral circuit over the second memory cell array.” This is a feature of non-elected Species III, see items 170a and 170b in Figures 11 and 12, for example. The elected Species I differs from Species III in that Species I includes only one peripheral circuit shared by the first memory cell array and the second memory cell array, see item 170 in Figures 4 and 5.
Claims 16-19 include additional details drawn to the embodiment of Figures 11-14 and/or depend on claim 15, and therefore, are also drawn to non-elected Species III.
Accordingly, claims 13-19 are considered withdrawn. Claims 1-12 are drawn to the elected Species I and are fully considered below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 9, and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jeong et al. (US 2024/0130131).
In reference to claim 1, Jeong et al. (US 2024/0130131), hereafter “Jeong,” discloses a memory device, with reference to Figure 14, comprising:
a first peripheral circuit comprising first page buffers, the first peripheral circuit having a cell region CA and a connection region PA, paragraphs 28 and 42;
a first memory cell array L1a over the first peripheral circuit, the first memory cell array comprising first bit lines UW1 electrically connected to corresponding ones of the first page buffers, paragraphs 95 and 29; and
a second memory cell array L1b over the first memory cell array and comprising second bit lines UW1, paragraphs 144, 145, and 152, which are electrically connected to corresponding ones of the first bit lines, by MPb, paragraph 149 and 150. In reference to claim 2, Jeong discloses wherein the first memory cell array comprises:
a first source line, 112 in Figure 14, in the cell region of the first peripheral circuit, paragraph 61;
first gate lines WLP over the first source line, paragraph 63;
first cell plugs CH (182, 184, 186) passing through the first gate lines, vertically between the first bit lines and the first source line, paragraph 69 and 70;
the first bit lines UW1 coupled to the first cell plugs;
first page buffer contacts CP2 in the connection region of the first peripheral circuit and electrically connected to the first page buffers, paragraph 29 (“The memory cell array MCA may be connected with … the page buffer circuit PBC through bit lines BL.”); and
first sub-bit lines UW3 electrically connecting the first page buffer contacts and the first bit lines, respectively, paragraphs 29, 94, and 95 (“the first upper wiring UW1 and the third upper wiring UW3 may be connected directly/indirectly,” paragraph 95).
In reference to claim 3, Jeong discloses the second memory cell array L1b comprises second bit lines UW1, second gate lines WLP, a second source line 112, second cell plugs CH (182, 184, 186) and second sub-bit lines UW3, Figure 14 and paragraphs 69, 70, 94, 95, and 145.
In reference to claim 9, Jeong discloses first gate transmission lines UW2 in Figure 14, in the connection region PA of the first memory cell array and which is electrically connected to the first gate lines WLP; and gate line contacts CP2 in the connection region of the first memory cell array and which is configured to transmit word line voltages to the first gate transmission lines, which are received from the first peripheral circuit, paragraphs 83 and 84.
In reference to claim 10, Jeong discloses second gate transmission lines UW2 in the connection region of the second memory cell array L1b and which are configured to electrically connect the second gate lines WLP and the first gate transmission lines, paragraphs 83, 84, and 145.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2024/0130131) in view of Konno et al. (US 2023/0062835).
In reference to claim 4, Jeong discloses the first source line, 112 in Figure 14, coupled to the first peripheral circuit L2.
Jeong does not disclose the first source line further includes spaced apart source bonding pads coupled to the first peripheral circuit.
Konno et al. (US 2023/0062835), hereafter “Konno,” discloses an analogous semiconductor device including teaching the first source line, 210 in Figure 3, further includes spaced apart source bonding pads, 220 in Figures 3 and 13, paragraphs 55, 58, 62, and 83.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first source line further includes spaced apart source bonding pads. One would have been motivated to do so in order to provide a support layer to prevent warpage of the semiconductor device, paragraph 58.
In reference to the bonding pads being coupled to the first peripheral circuit, Jeong discloses the source line bonded to the first peripheral circuit and Konno teaches the surface of the source line including the bonding pads, as addressed above. It results naturally from the combination of Jeong and Konno to include the pads of Konno on the source line of Jeong that the bonding pads are coupled to the first peripheral circuit.
In reference to claim 5, Jeong in view of Konno discloses the source bonding pads are in contact with an upper surface of a peripheral gap fill layer, 110 in Figure 14 of Jeong, which covers transistors in the first peripheral circuit, paragraph 60.
In reference to claim 6, Konno discloses each source bonding pad comprises a dielectric layer, paragraph 62.
In reference to claim 8, Konno discloses the source bonding pads, 220 in Figure 13, have a horizontal cross-sectional shape, which is at least one of: substantially square, substantially rectangular, substantially circular, and substantially oval, paragraph 84.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2024/0130131) in view of Konno et al. (US 2023/0062835) as applied to claim 4 above and further in view of Hwang et al. (US 2022/0108963).
In reference to claim 7, Jeong in view of Konno does not disclose each of the source bonding pads is configured of a plurality of different dielectric layers.
Hwang et al. (US 2022/0108963) discloses an analogous semiconductor device including teaching each of the source bonding pads, DP in Figures 1 and 5, is configured of a plurality of different dielectric layers, paragraphs 58 and 59. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for each of the source bonding pads to be configured of a plurality of different dielectric layers. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one fill material configuration for another, as suggested by Hwang, Figures 4 and 5.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2024/0130131) in view of Jung et al. (US 2021/0202458), Wu et al. (US 2021/0320121) and Lim (US 2022/0020767).
In reference to claim 11, Jeong does not disclose a bonding pad in the connection region of the first memory cell array and configured to transmit a source voltage generated in the first peripheral circuit to the first source line; a contact liner layer surrounding the bonding pad between the bonding pad and the first source line; a first source contact contacting the bonding pad by passing through sacrificial layers stacked in the connection region of the first memory cell array; and a second source contact in the connection region of the second memory cell array and configured to electrically connect the first source contact and the second source line.
Jung et al. (US 2021/0202458) discloses an analogous semiconductor device including a bonding pad, 170c in Figure 8, in the connection region of the first memory cell array and configured to transmit a source voltage generated in the first peripheral circuit to the first source line, paragraphs 40 and 63; a first source contact 164’ in Figure 9, and a second source contact 164 in the connection region of the second memory cell array and configured to electrically connect the first source contact and the second source line, paragraphs 104 and 105.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the device to include a bonding pad in the connection region of the first memory cell array and configured to transmit a source voltage generated in the first peripheral circuit to the first source line; a first source contact; and a second source contact in the connection region of the second memory cell array and configured to electrically connect the first source contact and the second source line. One would have been motivated to do so in order to pass a source line signal form the peripheral circuitry to the memory cell arrays, paragraphs 26, 27, 34, and 40.
Wu et al. (US 2021/0320121) discloses an analogous semiconductor device including teaching a bonding pad, 128 in Figure 1A, in the connection region of the first memory cell array and configured to transmit a source voltage generated in the first peripheral circuit to the first source line; a contact liner layer surrounding the bonding pad between the bonding pad and the first source line; paragraphs 32 and 67.
It would have been obvious to one or ordinary skill in the art before the effective filing date of the invention for the device to include a bonding pad in the connection region of the first memory cell array and configured to transmit a source voltage generated in the first peripheral circuit to the first source line, a contact liner layer surrounding the bonding pad between the bonding pad and the first source line. One would have been motivated to do so in order to provide a backside source contact with good adhesion, paragraph 32.
In reference to the first source contact contacting the bonding pad, Jung discloses the first source contact in electrical contact with the source line and Wu discloses the bonding pad in electrical contact with the source line, as addressed above. It results naturally from the combination of Jung and Wu that the first source contact is contacting (electrically) the bonding pad.
Lim (US 2022/0020767) discloses an analogous semiconductor device including teaching a first source contact 273 in Figure 9K (unlabeled in Figure 6), passing through sacrificial layers 220 stacked in the connection region of the first memory cell array, paragraph 74. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first source contact to pass through sacrificial layers stacked in the connection region of the first memory cell array. One would have been motivated to do so in order to insulate through vias in a compact wiring structure, paragraphs 3 and 74.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US 2024/0130131) in view of Kato (US 2023/0422522).
In reference to claim 12, Jeong does not disclose an external power pad exposed on an upper portion of the second memory cell array; a second power contact in the connection region of the second memory cell array and electrically connected to the external power pad; and a first power contact in the connection region of the first memory cell array and configured to transmit external power supplied through the external power pad to the first peripheral circuit.
Kato (US 2023/0422522) discloses an analogous semiconductor device including teaching an external power pad, 50 in Figure 1, exposed on an upper portion of the second memory cell array CH2; a second power contact 29 in the connection region of the second memory cell array and electrically connected to the external power pad; and a first power contact 19 in the connection region of the first memory cell array CH1 and configured to transmit external power supplied through the external power pad to the first peripheral circuit, paragraph 35.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for an external power pad to be exposed on an upper portion of the second memory cell array; a second power contact in the connection region of the second memory cell array and electrically connected to the external power pad; and a first power contact in the connection region of the first memory cell array and configured to transmit external power supplied through the external power pad to the first peripheral circuit. One would have been motivated to do so in order to power the peripheral circuitry, paragraphs 22 and 35.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ashidate et al. (US 2023/0397425), Park (US 2020/0105721), Ogawa et al. (US 2022/0139441), Huang et al. (US 2021/0134820), Park et al. (US 2020/0105735), Park (US 2020/0144242), Kanamori et al. (US 2020/0203329), Kim (KR 20230103773 A), and Futatsuyama et al. (US 2024/0284673) disclose related semiconductor memory structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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/BRYAN R JUNGE/ Primary Examiner, Art Unit 2897
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