DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 15 recites the limitation "the level shift register circuit and the latch circuit" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US Publication No. 2021/0111137).
Regarding claim 1, Chen discloses a semiconductor device comprising (Figure 7A):
a low voltage device (400) located on a first substrate (430) and driven with a first level voltage (paragraph 63)
a high voltage device (500) located on a second substrate (530), driven with a second level voltage higher than the first level voltage, and coupled to the low voltage device (paragraph 4)
wherein the low voltage device (400) includes a FinFET (peripheral device 450 low or high voltage, paragraph 63)
wherein the high voltage device (500) includes a planar FET (430 planar memory cells)
Regarding claim 2, Chen discloses the low voltage device (400) includes a plurality of first wiring layers (470) and a first interlayer insulating film (468) insulating some of the plurality of first wiring layers, wherein the high voltage device (500) includes a plurality of second wiring layers (562) and a second interlayer insulating film (568) insulating some of the plurality of second wiring layers (562), wherein the plurality of first wiring layers (470) have a pitch defined therebetween smaller than a pitch defined between the plurality of second wiring layers (562) on a plane (the wirings on the right have a smaller pitch in the lower device compared to the wirings on the right in the upper device).
Regarding claim 3, Chen discloses the low voltage device (400) includes a plurality of first wiring layers (470), wherein the high voltage device (500) includes a plurality of second wiring layers (562), wherein the plurality of first wiring layers (470) have a wire width smaller than a wire width of the plurality of second wiring layers (562) on a plane.
Regarding claim 4, Chen discloses the low voltage device (400) is located on a first surface of the first substrate (430), wherein the high voltage device (500) is located on a first surface of the second substrate (530) facing the first surface of the first substrate (430), wherein the first surface of the first substrate and the first surface of the second substrate (530) are coupled to and bonded (688) to each other (paragraph 106).
Regarding claim 5, Chen discloses the low voltage device (400) includes a first bonding structure (690 lower), wherein the high voltage device (500) includes a second bonding structure (690 upper) coupled with the first bonding structure as the first surface of the first substrate (430) and the first surface of the second substrate (530) face each other.
Regarding claim 6, Chen discloses the low voltage device (400) and the high voltage device (500) are electrically connected to each other by the first bonding structure (690 lower) and the second bonding structure (690 upper).
Regarding claim 7, Chen discloses the first bonding structure and the second bonding structure contain a conductive metal (486/586).
Regarding claim 8, Chen discloses the low voltage device (400) is located on a first surface of the first substrate (430), wherein the high voltage device (500) is located on a first surface of the second substrate (530) facing the first surface of the first substrate (430), wherein the low voltage device (400) includes a first bonding structure (690 lower), wherein the high voltage device (500) includes a second bonding structure (690 upper)facing and coupled to the first bonding structure, wherein the semiconductor device further includes a pad structure (466) located on a second surface of the first substrate opposite to the first surface of the first substrate or on a second surface of the second substrate opposite to the first surface of the second substrate, wherein at least some of the first and second bonding structures (688/586/486) are electrically connected to the pad structure (466).
Regarding claim 9, Chen discloses the low voltage device (400) is located on a first surface of the first substrate (430), wherein the high voltage device (500) is located on a first surface of the second substrate (530) facing the first surface of the first substrate (430), wherein the low voltage device (400) includes a first FEOL structure (430) including the FinFET (450) and a first BEOL structure (430) including a plurality of first wiring layers (470), wherein the high voltage device (500) includes a second FEOL structure (530) including the planar FET (430) and a second BEOL structure (578) including a plurality of second wiring layers (562), wherein the semiconductor device further includes a pad structure (466) located on a second surface of the first substrate opposite to the first surface of the first substrate, wherein the low voltage device (400) includes a via (472) extending through the first substrate and the first FEOL structure (430) and electrically connecting the pad structure (466) and the low voltage device or the second BEOL structure (578) to each other.
Regarding claim 10, Chen discloses the low voltage device (400) is located on a first surface of the first substrate (430), wherein the high voltage device (500) is located on a first surface of the second substrate (530) facing the first surface of the first substrate (430), wherein the low voltage device (400) includes a first FEOL structure (430) including the FinFET (450) and a first BEOL structure (430) including a plurality of first wiring layers (470), wherein the high voltage device (500) includes a second FEOL structure (530) including the planar FET (430) and a second BEOL structure (530) including a plurality of second wiring layers, wherein the semiconductor device further includes a pad structure (466) located on a second surface of the second substrate opposite to the first surface of the second substrate, wherein the high voltage device (500) includes a via (340) extending through the second substrate and the second FEOL structure and electrically connecting the pad structure (466) and the first FEOL structure (430) or the second FEOL structure (578) to each other.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Publication No. 2021/0111137) in view of Kai et al. (US Publication No. 2020/0286905).
Regarding claim 11, Chen discloses the limitations as discussed in the rejection of claim 1 above. Chen is silent regarding a pad structure electrically connected to the low voltage device and the high voltage device, wherein the pad structure includes: an input/output pad electrically connected to at least one of the low voltage device and the high voltage device; a pad insulating film covering a portion of the input/output pad and exposing at least a portion of the input/output pad; and a solder ball electrically connected to the input/output pad by being in direct contact with the input/output pad in an area where the input/output pad is exposed. However, Kai discloses an input/output pad (338) electrically connected to at least one of the low voltage device (96) and the high voltage device (20); a pad insulating film (165) covering a portion of the input/output pad and exposing at least a portion of the input/output pad (338); and a solder ball (995) electrically connected to the input/output pad by being in direct contact with the input/output pad in an area where the input/output pad is exposed (Figure 33D).
Claims 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Publication No. 2021/0111137) in view of Yamazaki et al. (US Publication No. 2021/0134920).
Regarding claim 12, Chen discloses a display driver including a semiconductor device, the display driver comprising:
a first circuit driven with a first level voltage (400) (paragraph 63)
a second circuit driven with a second level voltage higher (500) than the first level voltage (paragraph 4), wherein the second circuit faces the first circuit and is coupled to and bonded (688) to the first circuit
wherein the first circuit includes a low voltage device (400) including a FinFET (450)
wherein the second circuit includes a high voltage device (500) including a planar FET (430)
Chen is silent regarding the semiconductor device being included in a display driver. However, Yamazaki discloses a display panel with a driver circuit SD1. It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the device of Chen to be driven by a display driver, as taught by Yamazaki, since it can provide improved applications supplying image signals, resulting in a novel display panel that is convenient and reliable (paragraph 144).
Regarding claim 13, Chen discloses the low voltage device (400) includes a plurality of first wiring layers (470) and a first interlayer insulating film (468) insulating some of the plurality of first wiring layers, wherein the high voltage device (500) includes a plurality of second wiring layers (562) and a second interlayer insulating film (568) insulating some of the plurality of second wiring layers (562), wherein the plurality of first wiring layers (470) have a pitch defined therebetween smaller than a pitch defined between the plurality of second wiring layers (562) on a plane (the wirings on the right have a smaller pitch in the lower device compared to the wirings on the right in the upper device).
Regarding claim 14, Chen discloses the low voltage device (400) includes a plurality of first wiring layers (470), wherein the high voltage device (500) includes a plurality of second wiring layers (562), wherein the plurality of first wiring layers (470) have a wire width smaller than a wire width of the plurality of second wiring layers (562) on a plane.
Regarding claim 15, Yamazaki discloses the shift register circuit and the latch circuit include the low voltage device, wherein the level shifter circuit and the digital analog converter circuit include the high voltage device (paragraph 145). As discussed above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Chen in view of Yamazaki.
Regarding claim 16, Chen discloses the low voltage device (400) includes a first bonding structure (690 lower), wherein the high voltage device (500) includes a second bonding structure (690 upper) coupled with the first bonding structure as the first surface of the first substrate (430) and the first surface of the second substrate (530) face each other, wherein the low voltage device (400) and the high voltage device (500) are electrically connected to each other by the first bonding structure (690 lower) and the second bonding structure (690 upper).
Regarding claim 17, Chen discloses the first bonding structure and the second bonding structure contain a conductive metal (486/586).
Regarding claim 18, Chen discloses the low voltage device (400) is located on a first surface of the first substrate (430), wherein the high voltage device (500) is located on a first surface of the second substrate (530) facing the first surface of the first substrate (430), wherein the low voltage device (400) includes a first bonding structure (690 lower), wherein the high voltage device (500) includes a second bonding structure (690 upper)facing and coupled to the first bonding structure, wherein the semiconductor device further includes a pad structure (466) located on a second surface of the first substrate opposite to the first surface of the first substrate or on a second surface of the second substrate opposite to the first surface of the second substrate, wherein at least some of the first and second bonding structures (688/586/486) are electrically connected to the pad structure (466).
Regarding claim 19, Chen discloses the low voltage device (400) is located on a first surface of the first substrate (430), wherein the high voltage device (500) is located on a first surface of the second substrate (530) facing the first surface of the first substrate (430), wherein the low voltage device (400) includes a first FEOL structure (430) including the FinFET (450) and a first BEOL structure (430) including a plurality of first wiring layers (470), wherein the high voltage device (500) includes a second FEOL structure (530) including the planar FET (430) and a second BEOL structure (578) including a plurality of second wiring layers (562), wherein the semiconductor device further includes a pad structure (466) located on a second surface of the first substrate opposite to the first surface of the first substrate, wherein the low voltage device (400) includes a via (472) extending through the first substrate and the first FEOL structure (430) and electrically connecting the pad structure (466) and the low voltage device or the second BEOL structure (578) to each other.
Regarding claim 20, Chen discloses the low voltage device (400) is located on a first surface of the first substrate (430), wherein the high voltage device (500) is located on a first surface of the second substrate (530) facing the first surface of the first substrate (430), wherein the low voltage device (400) includes a first FEOL structure (430) including the FinFET (450) and a first BEOL structure (430) including a plurality of first wiring layers (470), wherein the high voltage device (500) includes a second FEOL structure (530) including the planar FET (430) and a second BEOL structure (530) including a plurality of second wiring layers, wherein the semiconductor device further includes a pad structure (466) located on a second surface of the second substrate opposite to the first surface of the second substrate, wherein the high voltage device (500) includes a via (340) extending through the second substrate and the second FEOL structure and electrically connecting the pad structure (466) and the first FEOL structure (430) or the second FEOL structure (578) to each other.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liu (US Publication No. 2020/0328186) discloses bonding high and low voltage devices with an exposed input/output (1480) (Figure 14). Huo et al. (US Publication No. 2020/0006371) discloses bonding high and low voltage devices with different pitch wirings (Figure 1A).
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/N.R.P/ 6/8/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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