DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Mariani et al. US 2022/0020756 and Citla et al. US 2018/0005850.
Re claim 1, Mariani teaches a memory device (10, fig14 and 16, [25]) comprising:
a first memory cell (90 left, fig16, [75]) having a first top electrode (72 adjacent to left 56, fig16, [75]) separated from a first bottom electrode (56 left, fig16, [47]) by a first ferroelectric region (70 around left 56, fig16, [62]);
a second memory cell (90 adjacent to left 90, fig16, [75]) having a second top electrode (72 of 90 adjacent to left 90, fig16, [75]) separated from a second bottom electrode (56 of 90 adjacent to left 90, fig16, [47]) by a second ferroelectric region (70 of 90 adjacent to left 90, fig16, [62]); and
a dielectric material (48, 50, fig16, [40]) separating the first bottom electrode from the second bottom electrode (48 and 50 formed between 56, fig16).
Mariani does not explicitly show the dielectric material is a material with a dielectric constant equal to or less than 3.5.
Citla teaches high etch selectivity for silicon oxycarbide ([50]) with respect to silicon oxide and silicon nitride.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mariani and Citla to use silicon oxycarbide with a dielectric constant less than 3 as the material for 48 and 50. The motivation to do so is to prevent over etch of layer 48/50 during removal of silicon dioxide layer 42 and 52 in fig7A and 7B with desired etch profiles (Citla, [50]).
Re claim 2, Mariani modified above teaches the memory device of claim 1, wherein electrode material of the first top electrode, the first bottom electrode, the second top electrode, or the second bottom electrode includes one or more of titanium (56, 72, fig16, [47, 67]), titanium nitride, or tungsten nitride.
Re claim 3, Mariani modified above teaches the memory device of claim 1, wherein ferroelectric material of the first ferroelectric region or the second ferroelectric region includes hafnium oxide (70, fig16, [63]), zirconium oxide (70, fig16, [63]), or a combination of hafnium oxide and zirconium oxide.
Re claim 4, Mariani modified above teaches the memory device of claim 1, wherein the low-k dielectric material includes one or more of silicon oxide, silicon oxycarbide (48, 50 as SiOC, fig16), fluorine doped silicon glass, or porous silicon oxide.
Re claim 5, Mariani modified above teaches the memory device of claim 1, wherein the memory device includes a plate (78, fig16, [75]) coupled to the first top electrode and to the second top electrode (72, fig16, [75]).
Re claim 6, Mariani modified above teaches the memory device of claim 5, wherein the low-k dielectric material (48, 50 as SiOC , fig16, [40]): separates the first top electrode (72 of 90 left, fig16, [75]) from the second top electrode (72 adjacent to 50 in second memory cell 90, fig16, [75]); contacts the first bottom electrode (56 left, fig16, [47]) and the second bottom electrode (56 right, fig16, [47]) at a vertical level below the first top electrode (72 adjacent to left 56, fig16, [75]) and the second top electrode (72 adjacent to right 56, fig16, [75]); and extends from the vertical level at which the low-k dielectric material (48, 50 as SiOC, fig16, [40]) contacts the first bottom electrode (56 left, fig16, [47]) and the second bottom electrode (56 right, fig16, [47]) to the plate (78, fig16, [75]).
Re claim 7, Mariani modified above teaches the memory device of claim 5, wherein the first top electrode (72 on left side of 98 left, fig14 and 16, [75]) and the second top electrode (72 on right side of 98 left, fig14 and 16, [75]) are configured as a single continuous electrode (72, fig14) located on and extending vertically from the low-k dielectric material (48, 50 as SiOC, fig16, [40]) to contact the plate (78, fig16, [75]).
Re claim 8, Mariani modified above teaches the memory device of claim 5, wherein the memory device includes a leaker (46, fig16, [41]) on and contacting the first bottom electrode (56 left, fig16, [47]) and located under and coupled to the plate (78, fig16, [75]).
Re claim 9, Mariani teaches a memory device (10, fig14 and 16, [25]) comprising:
access lines (100, fig17 and 18, [94]);
digit lines (102, fig17 and 18, [94]); and
an array of memory cells (90, fig16 and 18, [75]), each memory cell having an access transistor (12, fig18, [25]) coupled to one of the access lines (100, fig17 and 18, [94]) and having a storage structure (82, fig18, [94]) coupled to one of the digit lines (102, fig17 and 18, [94]) via the access transistor (12, fig18, [25]),
the storage structure (82, fig16 and 18, [94]) including a top electrode (72, fig16, [75]) separated from a bottom electrode (56, fig16, [47]) by a ferroelectric region (70, fig16, [63]), the bottom electrode (56 left, fig16, [47]) separated from a bottom electrode of an adjacent memory cell (56 right of another 90, fig16, [47]) by a dielectric material (48-50 or 48-50-94, fig16, [40, 86]).
Mariani does not explicitly show the dielectric material is a material with a dielectric constant equal to or less than 3.5.
Citla teaches high etch selectivity for silicon oxycarbide ([50]) with respect to silicon oxide and silicon nitride.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mariani and Citla to use silicon oxycarbide with a dielectric constant less than 3 as the material for 48, 50 and 94. The motivation to do so is to prevent over etch of layer 48, 50 and 94 during removal of silicon dioxide layer 42 and 52 in fig5A and 7B for the space filled by 70/72 with desired etch profiles (Citla, [50]).
Re claim 10, Mariani modified above teaches the memory device of claim 9, wherein each memory cell is positioned within a container structure with three adjacent memory cells (fig14).
Re claim 11, Mariani modified above teaches the memory device of claim 10, wherein the array has multiple container structures separated by isolation dielectrics (94, fig14A, [86]), each container structure containing four memory cells adjacent to each other (fig14) with bottom electrodes of storage structures of the adjacent memory cells separated by the low-k dielectric material (48 and 50 as SiOC, fig16, [40]).
Re claim 12, Mariani modified above teaches the memory device of claim 9, wherein the low-k dielectric material (48, 50 and 94 as SiOC, fig16, [40, 86]) separates the ferroelectric region (70 of 90, fig16) from a ferroelectric region of the adjacent memory cell (70 of adjacent 90, fig16) and separates the top electrode (72 of 90, fig16, [75]) from a top electrode of the adjacent memory cell (72 of adjacent 90, fig16, [75]).
Re claim 13, Mariani modified above teaches the memory device of claim 12, wherein the low-k dielectric material (48, 50 and 94 as SiOC, fig16, [40, 86]) extends from a bottom level of the bottom electrode (56 left, fig16, [47]) to a plate (78, fig16, [75]) positioned on a top surface of the top electrode (72 of 90, fig16, [75]) and a top surface of the top electrode of the adjacent memory cell (72 of adjacent 90, fig16, [75]).
Re claim 14, Mariani modified above teaches the memory device of claim 9, wherein: the low-k dielectric material (48, 50 and 94 as SiOC, fig14 and 16, [40, 86]) separates the ferroelectric region (70 of 90 in region 60b left of center 60a, fig16, [63]) from a ferroelectric region of the adjacent memory cell (70 of 90 in region 60b right of center 60a, fig16, [63]); the top electrode (72, fig16, [75]) is a top electrode of the adjacent memory cell (90, fig14, 16); and the top electrode (72, fig16, [75]) is positioned on the low-k dielectric material (48, 50 and 94, fig14, 16, [40, 86]).
Re claim 15, Mariani modified above teaches the memory device of claim 9, wherein the low-k dielectric material (48, 50 and 94, fig14, 16, [40, 86]) separates the bottom electrode (56 of 90, fig16, [47]) from the bottom electrode of the adjacent memory cell (56 of adjacent 90, fig16, [47]) by a distance equal to or less than about ten nanometers (width between 54/56 about 10nm (P1-W1), fig3A, [44]).
Re claim 16, Mariani teaches a method of forming a memory device (10, fig14 and 16, [25]), the method comprising:
forming a first memory cell (90 left, fig16 and 18, [75]) having a first top electrode (72 of 90 left, fig16, [75]) separated from a first bottom electrode (56 of 90 left, fig16, [47]) by a first ferroelectric region (70 of 90 left, fig16, [63]);
forming a second memory cell (90 adjacent to 90 left, fig16 and 18, [75]) having a second top electrode (72 of 90 adjacent to 90 left, fig16, [75]) separated from a second bottom electrode (56 of 90 adjacent to 90 left, fig16, [47]) by a second ferroelectric region (70 of 90 adjacent to 90 left, fig16, [63]); and
forming a dielectric material (48, 50, fig16, [40, 86]) separating the first bottom electrode (56 of 90 left, fig16, [47]) from the second bottom electrode (56 of 90 adjacent to 90 left, fig16, [47]).
Mariani does not explicitly show the dielectric material is a material with a dielectric constant equal to or less than 3.5.
Citla teaches high etch selectivity for silicon oxycarbide ([50]) with respect to silicon oxide and silicon nitride.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mariani and Citla to use silicon oxycarbide with a dielectric constant less than 3 as the material for 48, 50 and 94. The motivation to do so is to prevent over etch of layer 48, 50 and 94 during removal of silicon dioxide layer 42 and 52 in fig5A and 7B for the space filled by 70/72 with desired etch profiles (Citla, [50]).
Allowable Subject Matter
Claim 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to increase memory cell density.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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