Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments directed to the newly amended claims filed 6/5/2026 have been fully considered but they are not persuasive.
Applicant contends that the amened claims 1 and 19 are patentable over the prior art because the recited vertical segments allow dopant to be restricted to specific areas while avoiding unwanted vertical spread. However, applicant is attempting to import functional limitations from the specification that are not structurally or methodically capture by the actual language of the claims.
Specifically, Claim 1 recites a “first vertical segment” filled with mid-material and “second vertical segment” filled with an insulative material within an internal volume of a cylinder. Notably, the claim fails to recite any definite spatial boundaries, vertical coordinates, dimensions, or relative positioning for these segments , nor does it structurally restrict the segments to specific locations relative to the select-gate transistors.
Because the claim is drafted in an open-ended manner and lacks restrictive structural geography, it remains broad enough to encompass any configuration where an insulative material or plug is positioned at any vertical location along a channel column. Accordingly, Lee, which discloses out diffusing dopants from an internal core material along a vertical column structure, meets the literal terms of the claim. The substance of the rejection is therefore maintained in the following rejections.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-18 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20170012051 A1).
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CLAIM 1. Lee teaches a method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating different-composition first tiers and second tiers (Figs. 1A&B), channel-material strings CH extending through the first and second tiers ML. , the channel material CH of an upper portion of each of the channel- material strings being part of multiple vertically stacked individual select-gate transistors ¶3-361 in a finished-circuitry construction (Figs. 1A&B), a lower portion of the channel-material strings being part of memory-cell strings in the finished-circuitry construction, the upper portion of the channel-material strings individually comprising a cylinder comprising the channel material of the individual select-gate transistors USL (Figs. 1A&B & ¶32-36);
forming a mid-material 125/325 within an internal volume of the cylinder radially-inside of and in direct physical contact (Fig. 7A – material may be in “direct physical contact”) with the channel material, the mid-material material comprising conductivity-increasing dopant therein (Fig. 2A), the mid material filling a first vertical segment [Note: The limitation is open ended, not defining explicit boundaries.] of the internal volume of the cylinder, a second vertical segment [Note: The limitation is open ended, not defining explicit boundaries.] of the internal volume of the cylinder being filed with an insulative material (Fig. 3D – Note: first and second vertical segments may be arbitrarily define, thus there is no clear distinction over the claimed subject matter and the prior art.); and
out-diffusing the conductivity-increasing dopant from the mid-material into the channel material of the cylinder and the individual select-gate transistors , the mid-material being insulative or semiconductive (doped oxide) in the finished-circuitry construction (¶74 & Figs 3D, 5B, 7A-B).
5. Lee teaches a method of claim 1 wherein the channel material of the upper portion of the channel-material strings is of different composition from that of the mid-material but for at least one of quantity or presence of the conductivity-increasing dopant (¶74).
CLAIM 6. Lee teaches a method of claim 1 wherein, the first tiers in an upper portion of the stack comprise the select gates of the select-gate transistors in the finished-circuitry construction; the mid-material within individual of the cylinders is laterally-adjacent at least one of the first tiers in the upper portion of the stack; and the mid-material has at least one of a top or a bottom that is between immediately-vertically-adjacent of the first tiers in the upper portion of the stack (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 7. Lee teaches a method of claim 6 wherein the at least one of the top or the bottom is the top (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 8. Lee teaches a method of claim 6 wherein the at least one of the top or the bottom is the bottom (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 9. Lee teaches a method of claim 1 wherein, the first tiers in an upper portion of the stack comprise the select gates of the select-gate transistors in the finished-circuitry construction; and the mid-material within individual of the cylinders is laterally-adjacent only one of the first tiers in the upper portion of the stack (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 10. Lee teaches a method of claim 9 wherein the mid-material within the individual cylinders has a top that is elevationally-coincident with a top of said only one first tier (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 11. Lee teaches a method of claim 9 wherein the mid-material within the individual cylinders has a bottom that is elevationally-coincident with a bottom of said only one first tier (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 12. Lee teaches a method of claim 11 wherein the mid-material within the individual cylinders has a top that is elevationally-coincident with a top of said only one first tier (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 13. Lee teaches a method of claim 9 wherein the mid-material has at least one of a top or a bottom that is between immediately-vertically- adjacent of the first tiers in the upper portion of the stack (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 14. Lee teaches a method of claim 13 wherein the at least one of the top or the bottom is the top (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 15. Lee teaches a method of claim 13 wherein the at least one of the top or the bottom is the bottom (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 16. Lee teaches a method of claim 1 wherein, the first tiers in an upper portion of the stack comprise the select gates of the select-gate transistors in the finished-circuitry construction; and the mid-material within individual of the cylinders is laterally-adjacent multiple of the first tiers in the upper portion of the stack (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 17. Lee teaches a method of claim 16 wherein the mid-material within the individual cylinders has a top that is elevationally-coincident with a top of an uppermost of said multiple first tiers (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
CLAIM 18. Lee teaches a method of claim 16 wherein the mid-material within the individual cylinders has a bottom that is elevationally-coincident with a bottom of a lowest of said multiple first tiers (Figs. 1-7 – The claimed structural language is merely descriptive and imparts no functional or manipulative limitations that distinguish the method from Lee.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20170012051 A1).
CLAIM 2. Lee teaches a method of claim 1 however may be silent upon wherein the specific concentration of the conductivity-increasing dopant in the mid-material before and after the out-diffusing is 1 x 1018 atoms/cm3 to 1 x 1020.5 atoms/cm3.
It would have been obvious to one of ordinary skill in the art to arrive at a concentration of 1 x 10¹⁸ atoms/cm³ to 1 x 1020.5 atoms/cm³ through routine experimentation. In the field of semiconductor manufacturing, dopant concentration is a well-known result-effective variable that directly dictates device parameters such as conductivity, threshold voltage, and junction depth. Selecting an optimal concentration is a matter of routine optimization to achieve desired performance characteristics. Because the claimed range falls within or is suggested by functional concentrations known in the art, and there is no evidence that this specific range yields unexpected results or is critical to the operation of the device, it is not inventive to discover these workable parameters. Discovering the optimum value of a result-effective variable through routine calculation or experimentation remains a standard application of prior art teachings. See MPEP § 2144.05; In re Boesch, 617 F.2d 272 (CCPA 1980).
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 3. Lee teaches a method of claim 2 however may be silent upon wherein the specific concentration of the conductivity-increasing dopant in the mid-material before the out-diffusing is 1 x 10185 atoms/cm3 to 1 x 1020.5 atoms/cm3 and after the out-diffusing is 1 x 1018 atoms/cm3 to 1 x 1020 atoms/cm3.
It would have been obvious to one of ordinary skill in the art to arrive at a concentration through routine experimentation. In the field of semiconductor manufacturing, dopant concentration is a well-known result-effective variable that directly dictates device parameters such as conductivity, threshold voltage, and junction depth. Selecting an optimal concentration is a matter of routine optimization to achieve desired performance characteristics. Because the claimed range falls within or is suggested by functional concentrations known in the art, and there is no evidence that this specific range yields unexpected results or is critical to the operation of the device, it is not inventive to discover these workable parameters. Discovering the optimum value of a result-effective variable through routine calculation or experimentation remains a standard application of prior art teachings. See MPEP § 2144.05; In re Boesch, 617 F.2d 272 (CCPA 1980).
CLAIM 4. Lee teaches a method of claim 1 however may be silent upon the capability of wherein the channel material of the upper portion of the channel-material strings is of the same composition as that of the mid-material but for one of quantity or presence of the conductivity-increasing dopant.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to select a semiconductor material which may be the same as the channel material (e.g. silicon, which is a known solid phase dopant carrier material), since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20170012051 A1) in view of Said (US 20210193674 A1).
CLAIM 19. Lee teaches a method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating different-composition first tiers and second tiers, channel-material strings extending through the first and second tiers, the channel material of an upper portion of each of the channel- material strings being part of multiple individual select-gate transistors in a finished-circuitry construction, a lower portion of the channel-material strings being part of memory-cell strings in the finished-circuitry construction, the upper portion of the channel-material strings individually comprising a cylinder comprising the channel material of the individual select-gate transistors, insulating material being radially within the cylinder (Lee Figs. 1-7 ¶32-36);
forming a mid-material 125/325 in the opening atop the recessed insulating material within an internal volume of the cylinder radially-inside of and in direct physical contact (Fig. 7A) with the channel material, the mid-material material comprising conductivity-increasing dopant therein, the mid-material filling a first vertical segment within the internal volume of the cylinder and being in direct physical contact with the insulating material within a second vertical segment within the internal volume of the cylinder (Lee Figs. 1-7 ¶29);
and out-diffusing the conductivity-increasing dopant from the mid-material into the channel material of the cylinder and the individual select-gate transistors, the mid-material being insulative or semiconductive in the finished-circuitry construction (Lee Figs. 1-7 ¶29).
Lee may be silent upon vertically recessing the insulating material selectively relative to the channel material of the cylinder within an opening in which the cylinder and the insulating material are received. Lee discloses forming multi-tier NAND structures with cylindrical channel structures filled with a core material. Similarly, Said (¶[952-98] & Figs. 23I-K) teaches vertically recessing this core filler 62 material to form and locate a drain 63 within a channel shell. The difference between the claimed invention and the prior art is the specific application of performing a step of vertically recessing the core filling material.
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It would have been obvious to a PHOSITA at the time of the invention to modify Lee by incorporating the vertical recessing step taught by Said. Said teaches that this configuration improves contact between the channel and the drain, which is a well-known objective in multi-tier NAND manufacturing. Applying this known technique (recessing) to the device of Lee would yield the predictable result of increased surface area contact between the cylindrical semiconductor material and the drain material. Therefore, modifying Lee to include the recessed features taught by Said constitutes applying a known technique to a known device ready for improvement to yield predictable results, which is obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S. 398).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
6/17/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Lee - [0032] The conductive patterns LSL, WL, USL may surround the channel film CH, may include a lower selection line LSL, word-lines WLs, and an upper selection line USL, and may be arranged or stacked vertically. The lower selection line LSL may be disposed between the word-lines WLs and semiconductor substrate SUB. Although a single layer of the lower selection line LSL is shown, there may be multiple vertical layers of LSLs. The upper selection line USL may be disposed between the word-lines WLs and the bit line BL. Although a single layer of the upper selection line USL is shown, there may be multiple vertical layers of USLs.
[0033] Either the lower selection line LSL or the upper selection line USL may have a larger number of horizontal sub-divisions than those of each of the word-lines WLs. For example, as shown in FIG. 1A, each horizontal sub-division of each word-line WLs may be configured to surround two rows of the channel films CHs, and each horizontal sub-division of each upper selection line USL may be configured to surround a single row of the channel films CHs. In this case, the sub-divisions of the upper selection line USL may be separated from each other via the first slit SI1 and a second slit SI2. The first slit SI1 extends between the bit line BL and the substrate SUB, and the second silt extends between the bit line BL and the upper-most word-line.
[0034] The channel film CH may extend-through the conductive patterns LSL, WL, and USL. Additionally, although not shown in the drawing, there may be disposed a tunnel insulation film, a charge trap film and a charge block film between the channel film CH and conductive patterns LSL, WL, and USL. The tunnel insulation film may be constructed to contact the channel film CH and surround the channel film CH. The charge trap film may be constructed to contact the tunnel insulation film and surround the tunnel insulation film. The charge block film may be constructed to contact the charge trap film and surround the charge trap film. A top of each of the channel films CH may be electrically connected to the bit line BL.
[0035] In accordance with the above architecture, memory cells may be disposed respectively at intersections between the channel films CH and word-lines WLs. Lower selection transistors may be disposed respectively at intersections between the channel films CHs and lower selection line LSL.
[0036] Upper selection transistors may be disposed respectively at intersections between the channel films CHs and upper selection line USL. A single cell-string may be formed of a serial vertical arrangement of the lower selection transistor, memory cells, and upper selection transistor along a single channel film CH.
2 Said - [0095] Referring to FIG. 5G, the horizontal portion of the dielectric core layer 62L can be removed, for example, by a recess etch from above the top surface of the second semiconductor channel layer 602. Further, the material of the dielectric core layer 62L can be vertically recessed selective to the semiconductor material of the second semiconductor channel layer 602 into each memory opening 49 down to a depth between a first horizontal plane including the top surface of the cap spacer material layer 70 and a second horizontal plane including the bottom surface of the cap spacer material layer 70. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62.
Prosecution Insights