DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on February 3, 2026.
Claims 4, 12, and 19 are amended. No claims are canceled. No claims are added.
Applicant’s amendments to the specification submitted on February 3, 2026 are acknowledged and objections to the specification are withdrawn. No new matter is added as a result of the amendments.
Applicant’s amendments to claims 4, 12, and 19 overcome the 112(b) rejection set forth in the previous office action and therefore the 112(b) rejection is withdrawn.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1, 7, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang, et al (US 20170287568 A1), in view of Lee (US 20190019563 A1).
Regarding independent claim 1, Yang teaches an apparatus comprising:
a communication interface (FIG. 1B, between controller 202 and storage module 200; ¶ [0036]) configured to receive memory commands (¶ [0020]) for accessing a three-dimensional memory structure (FIG. 3; ¶ [0054]) having blocks (FIG. 6, Block 0..4; ¶ [0068]), each block having NAND strings and word lines connected to the NAND strings (FIG. 3, e.g., NAND string coupled to SGD0 and BL0; word lines WL0..WL47); and
one or more control circuits coupled to the communication interface (FIG. 2C, controller 270; ¶ [0051]), the one or more control circuits configured to connect to the three-dimensional memory structure (FIG. 2C, via Interface 292 and Flash memory control blocks such as State machine 296, Programming Circuits 294, etc.), the one or more control circuits configured to:
determine a magnitude for a program verify voltage (¶ [0051]) for a selected word line (¶ [0021]) in a selected sub-block in a selected block (in ¶ [0025], a block is analogous to a “section,” and therefore in ¶ [0024], a “sub-section” may be analogous to a sub-block);
apply the program verify voltage to the selected word line (FIG. 10, 1006); and
sense selected memory cells connected to the selected word line in response to application of the program verify voltage to the selected word line (FIG. 10, 1008).
Yang does not teach the magnitude for the program verify voltage depends on a programmed status of the word lines in one or more unselected sub-blocks in the selected block when the program verify voltage is applied to the selected word line; and
apply the program verify voltage having the magnitude that depends on the programmed status of the word lines in the one or more unselected sub-blocks to the selected word line.
Lee teaches the magnitude for the erase verify voltage depends on a programmed status of the word lines in one or more unselected sub-blocks in the selected block (FIG. 7; ¶ [0065-0071]).
Yang further teaches program disturb effects on the erase distribution may cause overlap with state A (see FIG. 4B; ¶ [0064]) and require program compensation (shifting) of program state distributions A to G to remedy the overlap (see FIG. 5; ¶ [0065-0067]), which in turn requires adjusting the program verify voltage (FIG. 9; ¶ [0072]) applied during programming the selected word line (FIG. 10; ¶ [0073]).
Therefore, Yang as modified by Lee teaches the magnitude for the program verify voltage (Yang) depends on a programmed status of the word lines in one or more unselected sub-blocks in the selected block (Lee) when the program verify voltage is applied to the selected word line (Yang); and
apply the program verify voltage (Yang) having the magnitude that depends on the programmed status of the word lines in the one or more unselected sub-blocks to the selected word line (Yang as modified by Lee).
Regarding independent claim 16, Yang teaches a non-volatile storage system, the system comprising:
a three-dimensional memory structure (FIG. 3; ¶ [0054]) having a plurality of blocks (FIG. 6, Block 0..4; ¶ [0068]), each block comprising NAND strings and data word lines connected to the NAND strings (FIG. 3, e.g., NAND string coupled to SGD0 and BL0), each block having multiple sub-blocks (in ¶ [0025], a block is analogous to a “section,” and therefore in ¶ [0024], a “sub-section” may be analogous to a sub-block);
means for determining a magnitude of a program verify voltage (FIG. 2C, controller 270; ¶ [0051]); and
means for verifying selected memory cells in a selected sub-block in the selected block based on the program verify voltage (FIG. 2B, Program Verify 155; FIG. 10, 1006).
Yang does not teach each sub-block contains a contiguous set of the data word lines of the block;
the means for determining a magnitude of a program verify voltage is based on a programmed completeness in one or more unselected sub-blocks of a selected block; and
the means for verifying selected memory cells in a selected sub-block in the selected block based on the program verify voltage is when the one or more unselected sub-blocks of the selected block have the programmed completeness.
Lee teaches each sub-block contains a contiguous set of the data word lines of the block (FIGS. 4A-4B, sub-blocks each occupy contiguous pages/word lines; ¶ [0048-0049]); and
the magnitude for the erase verify voltage depends on a programmed status of the word lines in one or more unselected sub-blocks in the selected block (FIG. 7; ¶ [0065-0071]).
Yang further teaches program disturb effects on the erase distribution may cause overlap with state A (see FIG. 4B; ¶ [0064]) and require program compensation (shifting) of program state distributions A to G to remedy the overlap (see FIG. 5; ¶ [0065-0067]), which in turn requires adjusting the program verify voltage (FIG. 9; ¶ [0072]) applied during programming the selected word line (FIG. 10; ¶ [0073]).
Therefore, Yang as modified by Lee teaches means for determining a magnitude of a program verify voltage (Yang) based on a programmed completeness in one or more unselected sub-blocks of a selected block (Lee); and
means for verifying selected memory cells in a selected sub-block in the selected block based on the program verify voltage (Yang) when the one or more unselected sub-blocks of the selected block have the programmed completeness (Yang as modified by Lee).
Regarding independent claims 1 and 16, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee into the method of Yang to include determining a verify voltage for a selected sub-block based on the program state of an adjacent unselected sub-block (Lee ¶ [0071]). The ordinary artisan would have been motivated to modify Yang in the above manner for the purpose of minimizing variation in threshold voltages of memory cells disposed adjacent to each other and, as a result, enhancing the performance of the semiconductor memory device (Lee ¶ [0072]).
Regarding claim 7, Yang as modified by Lee teaches the limitations of claim 1.
Yang as modified by Lee further teaches the one or more control circuits are further configured to:
select the selected word line for read after the selected memory cells have been program verified (Yang ¶ [0029]) for a first data state (Yang FIG. 4A, e.g., data state A of distribution chart 412) based on the program verify voltage having the magnitude that depended on the programmed status of the word lines in the one or more unselected sub-blocks in the selected block (Yang FIG. 10, 1002-1006; ¶ [0073] teaches “the program verify offset is applied to the default read conditions in order to generate the updated read conditions”);
determine a magnitude for a read reference voltage for the selected word line in the selected sub-block in the selected block (FIG. 10, 1002-1006; ¶ [0073] teaches “the program verify offset is applied to the default read conditions in order to generate the updated read conditions”), the magnitude for the read reference voltage depends on a programmed status of the word lines in the one or more unselected sub-blocks in the selected block when the read reference voltage is applied to the selected word line (FIG. 7; ¶ [0065-0071]); Yang teaches program disturb effects on the erase distribution may cause overlap with state A (see FIG. 4B; ¶ [0064]) and require program compensation (shifting) of program state distributions A to G to remedy the overlap (see FIG. 5; ¶ [0065-0067]), which in turn requires adjusting the program verify offset (FIG. 9; ¶ [0072]) used to adjust the read conditions (Abstract; FIG. 10));
apply the read reference voltage having the magnitude that depends on the programmed status of the word lines in the one or more unselected sub-blocks in the selected block to the selected word line during a sub-block mode (Lee teaches a magnitude for the erase verify voltage depends on a programmed status of the word lines in one or more unselected sub-blocks in the selected block (FIG. 7; ¶ [0065-0071]); Yang teaches program disturb effects on the erase distribution may cause overlap with state A (see FIG. 4B; ¶ [0064]) and require program compensation (shifting) of program state distributions A to G to remedy the overlap (see FIG. 5; ¶ [0065-0067]), which in turn requires adjusting the program verify offset (FIG. 9; ¶ [0072]) used to adjust the read conditions (Abstract; FIG. 10)); and
determine whether the selected memory cells connected to the selected word line have a threshold voltage of at least the first data state in response to application of the read reference voltage (Yang FIG. 10, 1008; Lee ¶ [0035]).
Regarding claim 19, Yang as modified by Lee teaches the limitations of claim 16.
Yang as modified by Lee further teaches means for determining a magnitude of a read reference voltage (Yang FIG. 10, 1002-1006; ¶ [0073] teaches “the program verify offset is applied to the default read conditions in order to generate the updated read conditions”) based on the programmed completeness in the one or more unselected sub-blocks of the selected block when the selected memory cells are read (FIG. 7; ¶ [0065-0071]); Yang teaches program disturb effects on the erase distribution may cause overlap with state A (see FIG. 4B; ¶ [0064]) and require program compensation (shifting) of program state distributions A to G to remedy the overlap (see FIG. 5; ¶ [0065-0067]), which in turn requires adjusting the program verify offset (FIG. 9; ¶ [0072]) used to adjust the read conditions (Abstract; FIG. 10)); and
means for reading the selected memory cells in the selected sub-block in the selected block based on the read reference voltage (Yang FIG. 10, 1008; Lee ¶ [0035]).
7. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190019563 A1) in view of Yang, et al (US 20170287568 A1).
Regarding independent claim 12, Lee teaches a method for operating a memory system, the method comprising:
determining a degree of programming in an unselected sub-block of a block (FIG. 7, S310, S330; ¶ [0070]), the block comprising a plurality of NAND strings and word lines (FIG. 3, block 300, strings coupled to BL1..BLm; word lines WL1..WLn), the block comprising the unselected sub-block and a selected sub-block (¶ [0047] teaches a block with a selected sub-block being erased, and an unselected sub-block), the selected sub-block comprising a first set of contiguous word lines, the unselected sub-block comprising a second set of contiguous word lines (FIGS. 4A-4B, sub-blocks each occupy different, contiguous pages/word lines; ¶ [0048-0049]);
Lee does not teach applying a program verify voltage to a selected word line in the selected sub-block, the program verify voltage having a magnitude that depends on the degree of programming in the unselected sub-block, the selected word line connected to selected memory cells; and
determining results of verifying the selected memory cells in response to application of the program verify voltage.
Therefore, Lee as modified by Yang teaches applying a program verify voltage to a selected word line (Yang FIG. 10, 1006) in the selected sub-block (in ¶ [0025], Yang teaches a block is analogous to a “section,” and therefore in ¶ [0024], a “sub-section” may be analogous to a sub-block such as the sub-blocks of Lee in FIGS. 4A-4B), the program verify voltage having a magnitude that depends on the degree of programming in the unselected sub-block, the selected word line connected to selected memory cells (Yang teaches program disturb effects on the erase distribution may cause overlap with state A (see FIG. 4B; ¶ [0064]) and require program compensation (shifting) of program state distributions A to G to remedy the overlap (see FIG. 5; ¶ [0065-0067]), which in turn requires adjusting the program verify voltage (FIG. 9; ¶ [0072]) applied during programming the selected word line (FIG. 10; ¶ [0073]), which can be accomplished by utilizing Lee’s erase verify voltage based on the degree of programming in the unselected sub-block); and
determining results of verifying the selected memory cells in response to application of the program verify voltage (Yang, FIG. 10, 1006, 1008).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Yang into the method of Lee to include shifting the program state distributions and corresponding program verify voltages (Yang ¶ [0065-0067]). The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of preventing the right tail of the erase state from overlapping with any other state (Yang ¶ [0065]; FIG. 5).
8. Claim 2-3, 8-11, 17-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang, et al (US 20170287568 A1), in view of Lee (US 20190019563 A1), and further in view of Moschiano, et al (US 20220415414 A1), hereinafter Moschiano.
Regarding claim 2, Yang as modified by Lee teaches the limitations of claim 1.
Yang as modified by Lee further teaches the one or more control circuits are further configured to:
establish the program verify voltage to have a first magnitude responsive to a percentage of unprogrammed word lines in the one or more unselected sub-blocks being below a first percentage (the “erased state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “first erase verify voltage” to determine Yang’s program verify voltage); and
establish the program verify voltage to have a second magnitude responsive to the percentage of unprogrammed word lines in the one or more unselected sub-blocks being above a second percentage that is at least as high as the first percentage (the “programmed state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “second erase verify voltage” to determine Yang’s program verify voltage).
Yang does not teach the second magnitude being greater than the first magnitude.
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075]).
That is, Yang as modified by Lee and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage. Therefore, Yang as modified by Lee and Moschiano teaches the second magnitude being greater than the first magnitude.
Regarding claim 3, Yang as modified by Lee teaches the limitations of claim 1.
Yang as modified by Lee further teaches the one or more control circuits are further configured to:
establish the program verify voltage to have a first magnitude responsive to the one or more unselected sub-blocks being open (the “erased state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “first erase verify voltage” to determine Yang’s program verify voltage) when the program verify voltage is to be applied to the selected word line; and
establish the program verify voltage to have a second magnitude responsive to the one or more unselected sub-blocks being closed (the “programmed state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “second erase verify voltage” to determine Yang’s program verify voltage) when the program verify voltage is to be applied to the selected word line.
Yang does not teach the second magnitude being greater than the first magnitude.
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075]).
That is, Yang as modified by Lee and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage. Therefore, Yang as modified by Lee and Moschiano teaches the second magnitude being greater than the first magnitude.
Regarding claim 8, Yang as modified by Lee teaches the limitations of claim 7.
Yang as modified by Lee further teaches the one or more control circuits are further configured to:
establish the read reference voltage to have a first magnitude responsive to the one or more unselected sub-blocks being open when the read reference voltage is to be applied to the selected word line (the “erased state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “first erase verify voltage” to determine Yang’s program verify voltage, which in turn determines the read conditions (Yang FIG. 10, 1002-1006; ¶ [0073])); and
establish the read reference voltage to have a second magnitude responsive to the one or more unselected sub-blocks being closed when the read reference voltage is to be applied to the selected word line (the “programmed state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “second erase verify voltage” to determine Yang’s program verify voltage which in turn determines the read conditions (Yang FIG. 10, 1002-1006; ¶ [0073])).
Yang does not teach the second magnitude being greater than the first magnitude.
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075]).
That is, Yang as modified by Lee and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage, which results in a higher read voltage. Therefore, Yang as modified by Lee and Moschiano teaches the second magnitude being greater than the first magnitude.
Regarding claim 9, Yang as modified by Lee teaches the limitations of claim 7.
Yang as modified by Lee further teaches the one or more control circuits are further configured to:
establish the read reference voltage to have a first magnitude responsive to a number of unprogrammed word lines in the one or more unselected sub-blocks being below a particular percentage when the read reference voltage is to be applied to the selected word line (the “erased state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “first erase verify voltage” to determine Yang’s program verify voltage, which in turn determines the read conditions (Yang FIG. 10, 1002-1006; ¶ [0073])); and
establish the read reference voltage to have a second magnitude responsive to the number of unprogrammed word lines in the one or more unselected sub-blocks being above the particular percentage when the read reference voltage is to be applied to the selected word line (the “programmed state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “second erase verify voltage” to determine Yang’s program verify voltage which in turn determines the read conditions (Yang FIG. 10, 1002-1006; ¶ [0073])),
Yang does not teach the second magnitude being greater than the first magnitude.
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075]).
That is, Yang as modified by Lee and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage, which results in a higher read voltage. Therefore, Yang as modified by Lee and Moschiano teaches the second magnitude being greater than the first magnitude.
Regarding claim 10, Yang as modified by Lee teaches the limitations of claim 1.
Lee further teaches the selected block comprises a first sub-block (FIG. 4A, e.g., SUB-BLOCK1) containing a first set of contiguous word lines (FIG. 4A, coupled to pages 1..16) including the selected word line, the first sub-block being the selected sub-block in the selected block;
the selected block comprises a second sub-block (FIG. 4A, e.g., SUB-BLOCK2) containing a second set of contiguous word lines (FIG. 4A, coupled to pages 17..32), the second sub-block being an unselected sub-block of the one or more unselected sub- blocks in the selected block;
Yang does not teach the one or more control circuits are further configured to:
establish the program verify voltage to have a first magnitude responsive to the second sub-block having less than or equal to a first percentage of word lines programmed when applying the program verify voltage to the selected word line;
establish the program verify voltage to have a second magnitude responsive to the second sub-block having more than the first percentage of word lines programmed but less than or equal to a second percentage of word lines programmed when applying the program verify voltage to the selected word line; and
establish the program verify voltage to have a third magnitude responsive to the second sub-block having more than the second percentage of word lines programmed but less than or equal to a third percentage of word lines programmed when applying the program verify voltage to the selected word line;
the first percentage is less than the second percentage;
the second percentage is less than the third percentage;
the first magnitude is less than the second magnitude; and
the second magnitude is less than the third magnitude.
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075])).
That is, Yang as modified by Lee and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage.
Therefore, Yang as modified by Lee and Moschiano teaches the one or more control circuits are further configured to:
establish the program verify voltage to have a first magnitude responsive to the second sub-block having less than or equal to a first percentage of word lines programmed when applying the program verify voltage to the selected word line (analogous to the example of Moschiano FIG. 7, 710A);
establish the program verify voltage to have a second magnitude responsive to the second sub-block having more than the first percentage of word lines programmed but less than or equal to a second percentage of word lines programmed when applying the program verify voltage to the selected word line (analogous to the example of Moschiano FIG. 7, 710B); and
establish the program verify voltage to have a third magnitude responsive to the second sub-block having more than the second percentage of word lines programmed but less than or equal to a third percentage of word lines programmed when applying the program verify voltage to the selected word line (analogous to the example of Moschiano FIG. 7, 710C);
the first percentage is less than the second percentage;
the second percentage is less than the third percentage;
the first magnitude is less than the second magnitude; and
the second magnitude is less than the third magnitude (because Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075]), if the first percentage of programmed word lines is less than the second percentage is less than the third percentage, the first magnitude will be less than the second magnitude will be less than the third magnitude).
Regarding claim 11, Yang as modified by Lee teaches the limitations of claim 1.
Lee further teaches the selected block comprises a first sub-block (FIG. 4B, e.g., SUB-BLOCK1) containing a first set of contiguous word lines (FIG. 4B, coupled to pages 1..8) including the selected word line, the first sub-block being the selected sub-block in the selected block;
the selected block comprises a second sub-block (FIG. 4B, e.g., SUB-BLOCK2) containing a second set of contiguous word lines (FIG. 4B, coupled to pages 9..16), the second sub-block being a first unselected sub-block of the one or more unselected sub-blocks in the selected block;
the selected block comprises a third sub-block (FIG. 4B, e.g., SUB-BLOCK3) containing a third set of contiguous word lines (FIG. 4B, coupled to pages 17-24), the third sub-block being a second unselected sub-block of the one or more unselected sub-blocks in the selected block.
Yang does not teach the one or more control circuits are further configured to:
establish the program verify voltage to have a first magnitude responsive the word line programmed status in the second sub-block and the third sub-block meeting a first fullness criterion; and
establish the program verify voltage to have a second magnitude responsive the word line programmed status in the second sub-block and the third sub-block meeting a second fullness criterion, the second fullness criterion having more word lines programmed than the first fullness criterion, the second magnitude being greater than the first magnitude.
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075])).
That is, Yang as modified by Lee and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage.
Therefore, Yang as modified by Lee and Moschiano teaches the one or more control circuits are further configured to:
establish the program verify voltage to have a first magnitude responsive the word line programmed status in the second sub-block and the third sub-block meeting a first fullness criterion (analogous to the example of Moschiano FIG. 7, 710A, resulting in a “first magnitude”); and
establish the program verify voltage to have a second magnitude responsive the word line programmed status in the second sub-block and the third sub-block meeting a second fullness criterion, the second fullness criterion having more word lines programmed than the first fullness criterion, the second magnitude being greater than the first magnitude (analogous to the example of Moschiano FIG. 7, 710B, resulting in a “second magnitude” greater than the first magnitude).
Regarding claim 17, Yang as modified by Lee teaches the limitations of claim 16.
Yang as modified by Lee further teaches the means for determining the magnitude of the program verify voltage based on the programmed completeness in the one or more unselected sub-blocks of the selected block is further configured to:
establish the program verify voltage to have a first magnitude responsive to the one or more unselected sub-blocks in the selected block meeting an openness criterion (the “erased state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “first erase verify voltage” to determine Yang’s program verify voltage); and
establish the program verify voltage to have a second magnitude responsive to the one or more unselected sub-blocks in the selected block meeting a closedness criterion (the “programmed state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “second erase verify voltage” to determine Yang’s program verify voltage).
Yang does not teach the second magnitude being greater than the first magnitude.
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075]).
That is, Yang as modified by Lee and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage. Therefore, Yang as modified by Lee and Moschiano teaches the second magnitude being greater than the first magnitude.
Regarding claim 18, Yang as modified by Lee teaches the limitations of claim 16.
Yang as modified by Lee further teaches the means for determining the magnitude of the program verify voltage based on the programmed completeness in the one or more unselected sub-blocks of a selected block is further configured to:
establish the program verify voltage to have a first magnitude responsive to the one or more unselected sub-blocks in the selected block being open (the “erased state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “first erase verify voltage” to determine Yang’s program verify voltage); and
establish the program verify voltage to have a second magnitude responsive to the one or more unselected sub-blocks in the selected block being closed (the “programmed state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “second erase verify voltage” to determine Yang’s program verify voltage).
Yang does not teach the second magnitude being greater than the first magnitude.
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075]).
That is, Yang as modified by Lee and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage. Therefore, Yang as modified by Lee and Moschiano teaches the second magnitude being greater than the first magnitude.
Regarding claim 20, Yang as modified by Lee teaches the limitations of claim 19.
Yang as modified by Lee further teaches the means for determining the magnitude of the read reference voltage based on the programmed completeness in the one or more unselected sub-blocks of the selected block when the selected memory cells are read is configured to:
establish the read reference voltage to have a first magnitude responsive to the one or more unselected sub-blocks in the selected block being open when the selected memory cells are read (the “erased state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “first erase verify voltage” to determine Yang’s program verify voltage, which in turn determines the read conditions (Yang FIG. 10, 1002-1006; ¶ [0073])); and
establish the read reference voltage to have a second magnitude responsive to the one or more unselected sub-blocks in the selected block being closed when the selected memory cells are read (the “programmed state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “second erase verify voltage” to determine Yang’s program verify voltage which in turn determines the read conditions (Yang FIG. 10, 1002-1006; ¶ [0073])).
Yang does not teach the second magnitude being greater than the first magnitude.
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075]).
That is, Yang as modified by Lee and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage, which results in a higher read voltage. Therefore, Yang as modified by Lee and Moschiano teaches the second magnitude being greater than the first magnitude.
Regarding claims 2-3, 8-11, 17-18, and 20, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Moschiano into the method of Yang to include adjusting the erase verify voltage threshold to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (Moschiano ¶ [0023]). The ordinary artisan would have been motivated to modify Yang in the above manner for the purpose of avoiding memory degradation that otherwise can be caused by memory erase operations by keeping the same pre-program voltage for all blocks being erased, while accounting for possible differences in their fully or partially programmed states by modifying the erase verify voltage threshold (Moschiano ¶ [0024]).
Regarding claims 2-3, 8-11, 17-18, and 20, Yang further teaches program disturb effects on the erase distribution may cause overlap with state A (see FIG. 4B; ¶ [0064]) and require program compensation (shifting) of program state distributions A to G to remedy the overlap (see FIG. 5; ¶ [0065-0067]), which in turn requires adjusting the program verify voltage (FIG. 9; ¶ [0072]) applied during programming the selected word line (FIG. 10; ¶ [0073]). When the method of Lee results in a higher erase verify voltage, the method of Yang would require a greater program compensation and greater program verify voltages for respective program states (reiterated from the independent claims for reference).
9. Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190019563 A1) in view of Yang, et al (US 20170287568 A1), and further in view of Moschiano, et al (US 20220415414 A1), hereinafter Moschiano.
Regarding claim 13, Lee as modified by Yang teaches the limitations of claim 12.
Lee as modified by Yang further teaches establishing the magnitude of the program verify voltage to be a first voltage responsive to a number of unprogrammed word lines in the unselected sub-block being below a particular percentage (the “erased state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “first erase verify voltage” to determine Yang’s program verify voltage); and
establishing the magnitude of the program verify voltage to be a second voltage responsive to the number of unprogrammed word lines in the unselected sub-block being above the particular percentage (the “programmed state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “second erase verify voltage” to determine Yang’s program verify voltage).
Lee does not teach the second magnitude being greater than the first magnitude.
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075]).
That is, Lee as modified by Yang and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage. Therefore, Lee as modified by Yang and Moschiano teaches the second magnitude being greater than the first magnitude.
Regarding claim 14, Lee as modified by Yang teaches the limitations of claim 12.
Lee as modified by Yang further teaches establishing the magnitude of the program verify voltage to be a first voltage responsive to the unselected sub-block being open (the “erased state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “first erase verify voltage” to determine Yang’s program verify voltage); and
establishing the magnitude of the program verify voltage to be a second voltage responsive to the unselected sub-block being closed (the “programmed state” of Lee in FIG. 7 and ¶ [0071], using Lee’s “second erase verify voltage” to determine Yang’s program verify voltage).
Moschiano teaches the erase verify voltage threshold can be adjusted to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (¶ [0071]; FIGS. 5-6), the voltage being adjusted negatively (becoming less) as the number of programmed pages becomes less (¶ [0075]).
That is, Lee as modified by Yang and Moschiano teaches the erase verify voltage increases as the number of programmed word lines increases, which in turn results in a higher program verify voltage. Therefore, Lee as modified by Yang and Moschiano teaches the second magnitude being greater than the first magnitude.
Regarding claims 13-14, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Moschiano into the method of Lee to include adjusting the erase verify voltage threshold to reflect the ratio of programmed/erased pages (or the ratio of programmed pages and the total number of pages) in the block being erased (Moschiano ¶ [0023]). The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of avoiding memory degradation that otherwise can be caused by memory erase operations by keeping the same pre-program voltage for all blocks being erased, while accounting for possible differences in their fully or partially programmed states by modifying the erase verify voltage threshold (Moschiano ¶ [0024]).
Regarding claims 13-14, Yang further teaches program disturb effects on the erase distribution may cause overlap with state A (see FIG. 4B; ¶ [0064]) and require program compensation (shifting) of program state distributions A to G to remedy the overlap (see FIG. 5; ¶ [0065-0067]), which in turn requires adjusting the program verify voltage (FIG. 9; ¶ [0072]) applied during programming the selected word line (FIG. 10; ¶ [0073]). When the method of Lee results in a higher erase verify voltage, the method of Yang requires a greater program compensation and greater program verify voltages for respective program states (reiterated from the independent claim for reference).
10. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yang, et al (US 20170287568 A1), in view of Lee (US 20190019563 A1), and further in view of Lee (US 20250022517 A1), hereinafter Lee ‘517.
Regarding claim 4, Yang as modified by Lee teaches the limitations of claim 1.
Yang does not teach apply a default voltage gap between the program verify voltage and a read reference voltage during a sub-block mode when the programmed status of the word lines in the one or more unselected sub-blocks in the selected block is the same during program verify and read of the selected word line, the program verify voltage being a voltage for verifying a first data state, and the read reference voltage being a voltage for reading the first data state; and
apply other than the default voltage gap between the program verify voltage and the read reference voltage during the sub-block mode when the programmed status of the word lines in the one or more unselected sub-blocks in the selected block is different during the read of the selected word line than during the program verify of the selected word line.
Lee ‘517 teaches setting read voltages corresponding to the verify voltages; and reading memory cells connected to a selected word line by sequentially applying the read voltages to the selected word line, wherein voltage differences between the read voltages and the verify voltages become larger as levels of the verify voltages becomes higher (¶ [0014]; FIG. 14).
Therefore, Yang as modified by Lee and Lee ‘517 teaches when the erase voltage increases based on the programmed status of the unselected sub-block (Lee FIG. 7), the voltage distributions shift higher (Yang FIG. 5), requiring a change in the read voltages based on the program verify voltage (Yang FIG. 10) as determined by the erase voltage increase, and the voltage difference (gap) between the program verify voltage and the read reference voltage increases (Lee ‘517 ¶ [0014]; FIG. 14).
Therefore, Yang as modified by Lee and Lee ‘517 teaches apply a default voltage gap (Lee ‘517, FIG. 13, 1Dv) between the program verify voltage (Lee ‘517, FIG. 13, 1Vf) and a read reference voltage (Lee ‘517, FIG. 13, 1Vr) during a sub-block mode when the programmed status of the word lines in the one or more unselected sub-blocks in the selected block is the same during program verify and read of the selected word line (e.g., when both the selected and unselected sub-blocks are in the erased state except the WL currently in the process of being programmed – see Lee FIG. 7), the program verify voltage being a voltage for verifying a first data state (Lee ‘517, FIG. 13, P1; Yang FIG. 4A, state A in distribution chart 412), and the read reference voltage being a voltage for reading the first data state (Lee ‘517 ¶ [0053]); and
apply other than the default voltage gap between the program verify voltage and the read reference voltage during the sub-block mode when the programmed status of the word lines in the one or more unselected sub-blocks in the selected block is different during the read of the selected word line than during the program verify of the selected word line (Yang further teaches program disturb effects on the erase distribution may cause overlap with state A (see FIG. 4B; ¶ [0064]) and require program compensation (shifting) of program state distributions A to G to remedy the overlap (see FIG. 5; ¶ [0065-0067]), which in turn requires adjusting the program verify voltage (FIG. 9; ¶ [0072]) applied during programming the selected word line (FIG. 10; ¶ [0073]) and the read conditions (FIG. 10, 1002-1006; ¶ [0073]). When the method of Lee results in a higher erase verify voltage, requiring program compensation (shifting) of program state distributions A to G to remedy the overlap, the method of Lee ‘517 results in the voltage difference (gap) between the program verify voltage and the read reference voltage increasing (Lee ‘517 ¶ [0014]; FIG. 14)). That is, the resultant “gap” is different from the default “gap.”
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee ‘517 into the method of Yang to include setting corresponding read and verify voltages such that voltage differences between the read voltages and the verify voltages become larger as levels of the verify voltages becomes higher (Lee ‘517 ¶ [0014]; FIG. 14). The ordinary artisan would have been motivated to modify Yang in the above manner for the purpose of improving the reliability of a read operation of memory cells (Lee ‘517 ¶ [0007]).
Allowable Subject Matter
11. Claims 5-6 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 5, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of apply a smaller voltage gap than the default voltage gap between the program verify voltage and the read reference voltage when more word lines are programmed in the one or more unselected sub-blocks in the selected block during the read than during the program verify of the selected word line.
Regarding claim 6, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of apply a larger voltage gap than the default voltage gap between the program verify voltage and the read reference voltage when fewer word lines are programmed in the one or more unselected sub-blocks in the selected block during the read than during the program verify of the selected word line.
Regarding claim 15, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of determining a degree of programming in the unselected sub-block of the block prior to a read while the selected memory cells connected to the selected word line still store data verified with the program verify voltage having the magnitude that depended on the degree of programming in the unselected sub-block at a time of program verify.
Conclusion
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/
Supervisory Patent Examiner, Art Unit 2827