Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20210143239 A1) hereafter referred to as Kim
In regard to claim 1 Kim teaches a display device [see “FIG. 1 is a plan view of a display device according to an embodiment” “FIG. 4 is a cross-sectional view showing an example section of a periphery of a bending area and a pixel according to an embodiment” “display area DA may include a plurality of pixels”] comprising:
a display element layer [“The pixel electrode ANO, the emission layer EL, and the cathode electrode CAT may constitute an organic light emitting device” “display area DA may include a plurality of pixels”] including a plurality of light emitting portions [see in plan view it is the region of “emission layer EL” where light is emitted], and a partition structure [“pixel defining layer PDL may be disposed on the pixel electrode ANO. The pixel defining layer PDL may include an opening for partially exposing the pixel electrode ANO”] separating the light emitting portions; and
a circuit layer including [“silicon transistor region AR1”] a plurality of transistors, a first insulation layer [“second interlayer dielectric ILD2” see also “second gate insulator GI2”] on the transistors and having a plurality of first holes [“second contact hole CNT2”] not overlapping the light emitting portions, a second insulation layer [“second via layer VIA2 may be stacked on only the display area DA”] on the first insulation layer and having a plurality of second holes [“second via layer VIA2 may form the sixth contact hole CNT6 exposing a portion of the connection electrode 161”] not overlapping the first holes, and a plurality of connection wiring portions [see 152, 161, ANO] electrically connecting the light emitting portions and the transistors, wherein:
each of the light emitting portions includes a light emitting element including a first electrode [“anode electrode ANO”], a second electrode [“cathode electrode CAT may be a common electrode”] facing the first electrode, and a light emitting layer [“emission layer EL may contain an organic material layer”] between the first electrode and the second electrode; and
each of the connection wiring portions includes:
a driving connection part [“second source/drain electrode 152 may be connected to the second source/drain area 111b of the silicon semiconductor layer 111 through the second contact hole CNT2”] electrically connected in correspondence to each of the transistors, and located in each of the first holes;
an emission connection part [“pixel electrode ANO may be an anode electrode”] electrically connected to the light emitting element, and having one side exposed [see the top and bottom of ANO are exposed by the hole in VIA2 ] in each of the second holes; and
an extension wiring [“the connection electrode 161 may be connected to the first and second source/drain electrodes 151 and 152 of the transistor disposed in the silicon semiconductor region AR1”] for connecting the emission connection part and the driving connection part.
In regard to claim 2 Kim teaches wherein the driving connection part in each of the first holes does not overlap [see Fig. 4 see 152 does not overlap EL] the light emitting portions.
In regard to claim 3 Kim teaches wherein the first holes do not overlap [see Fig. 4] the light emitting layer.
In regard to claim 4 Kim teaches wherein the first electrode is on [see Fig. 4] the second insulation layer, and an upper surface of the first electrode is exposed [see Fig. 4] in a light emitting opening defined in the partition structure, wherein the first holes do not overlap [see Fig. 4] the first electrode exposed in the light emitting opening.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20210143239 A1) hereafter referred to as Kim
In regard to claim 11 Kim teaches a display device [see “FIG. 1 is a plan view of a display device according to an embodiment” “FIG. 4 is a cross-sectional view showing an example section of a periphery of a bending area and a pixel according to an embodiment” “display area DA may include a plurality of pixels”] comprising:
a base layer [see “base substrate 101, a barrier layer 102, a buffer layer 103”];
a plurality of transistors [this limitation is satisfied by the AR1 transistors, (the Examiner notes that AR2 is a different type of transistor) see “silicon semiconductor layer 111 may be disposed in the silicon transistor region AR1. The silicon semiconductor layer 111 is a semiconductor layer for the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 and may form a channel of the corresponding transistors”] on the base layer;
an interlayer insulation layer [see “first interlayer dielectric ILD1” see also “second gate insulator GI2”] on the transistors;
a first insulation layer [“second interlayer dielectric ILD2” see also “second gate insulator GI2”] on the interlayer insulation layer, and having a plurality of first holes [“second contact hole CNT2”];
a second insulation layer [“second via layer VIA2 may be stacked on only the display area DA”] on the first insulation layer, and having a plurality of second holes [“second via layer VIA2 may form the sixth contact hole CNT6 exposing a portion of the connection electrode 161”] not overlapping the first holes;
a display element layer [“The pixel electrode ANO, the emission layer EL, and the cathode electrode CAT may constitute an organic light emitting device” “display area DA may include a plurality of pixels”] on the second insulation layer, and including a pixel definition layer [“pixel defining layer PDL may be disposed on the pixel electrode ANO. The pixel defining layer PDL may include an opening for partially exposing the pixel electrode ANO”] having light emitting openings and a plurality of light emitting elements [see “emission layer EL” ] in each of the light emitting openings; and
a plurality of connection wiring portions [see 152, 161, ANO] including a driving connection part [“second source/drain electrode 152 may be connected to the second source/drain area 111b of the silicon semiconductor layer 111 through the second contact hole CNT2”] in each of the first holes and electrically connected to the transistors, an emission connection part [“pixel electrode ANO may be an anode electrode”] exposed from each of the second holes and electrically connected to the light emitting elements, and an extension wiring [“the connection electrode 161 may be connected to the first and second source/drain electrodes 151 and 152 of the transistor disposed in the silicon semiconductor region AR1”] for connecting the driving connection part and the emission connection part, wherein the first holes do not overlap [see Fig. 4] the light emitting openings.
In regard to claim 12 Kim teaches wherein each of the light emitting elements comprises a first electrode [“cathode electrode CAT”], a second electrode [“pixel electrode ANO”] facing the first electrode, and a light emitting layer [“emission layer EL” ] between the first electrode and the second electrode, wherein the second electrode includes one end [see the left end of ANO is separated (i.e. it is on an opposite side) from the right end which is in CNT6] separated from a portion overlapping a second hole from among the second holes.
In regard to claim 13 Kim teaches wherein the separated one end of the second electrode is electrically connected [see ANO touches EL on the left and makes contact to 161 in the CNT6] to the emission connection part in each of the second holes.
In regard to claim 14 Kim teaches wherein a contact hole is defined in the interlayer insulation layer [“second source/drain electrode 152 may be connected to the second source/drain area 111b of the silicon semiconductor layer 111 through the second contact hole CNT2”], and an electrode pattern in the contact hole is further included [see Fig. 4], wherein each of the transistors is connected to [see Fig. 4] the driving connection part through the electrode pattern.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Aygun et al. (US 11854490 B1) hereafter referred to as Aygun
In regard to claim 5 Kim teaches wherein the display device is separated into a display region in which the light emitting portions are located [“display panel 100 may include a display area DA where a screen is displayed (e.g., a screen is configured to provide an image) and a non-display area NDA where a display is not realized (e.g., an image is not displayed)”] and a peripheral region on an outer periphery of the display device,
but does not specifically teach wherein a connection line portion connected to the light emitting portions adjacent to the peripheral region is longer than a connection line portion connected to the light emitting portions in a center of the display region.
See Aygun Fig. 12, Fig. 14 see the red (R), green (G), and blue (B) subpixels, see “As shown in FIG. 12, the density of emissive sub-pixels is consistent across the active area AA. To accommodate a uniform emissive sub-pixel density across the display (while still having gate driver circuitry in the active area), the density of the thin-film transistor sub-pixels may be greater than the density of the emissive sub-pixels. The thin-film transistor sub-pixels therefore occupy a smaller footprint than the emissive sub-pixels. The thin-film transistor sub-pixels may be consolidated in a central portion of the active area, resulting in an area at the periphery of the active area where emissive sub-pixels can overlap gate driver circuitry” “FIG. 14 is a cross-sectional side view of the display shown in FIG. 12” “As shown in FIG. 14, conductive paths 76 allow for each emissive sub-pixel 62 to not necessarily vertically overlap the respective thin-film transistor sub-pixel 64 by which it is controlled. Some of the emissive sub-pixels are shifted laterally relative to their controlling thin-film transistor sub-pixel. Emissive sub-pixels may be shifted laterally relative to their controlling thin-film transistor sub-pixel either away from a center of the active area or towards the center of the active area”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kim to include that wherein a connection line portion connected to the light emitting portions adjacent to the peripheral region is longer than a connection line portion connected to the light emitting portions in a center of the display region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is so that the region at the edge of the display does not have any driving units because all the driving units are only in the central region so that the space in the region at the edge of the display can be used for gate driver circuitry in order to save area.
In regard to claim 6 Kim does not specifically teach wherein the light emitting portions comprise a first light emitting portion, a second light emitting portion, and a third light emitting portion, which are configured to emit light of different wavelength regions from each other, wherein the first light emitting portion to the third light emitting portion constitute one light emitting unit, wherein a plurality of light emitting units each including the first to third light emitting portions are arranged in a first direction or in a second direction crossing the first direction.
See Kim “display area DA may include a plurality of pixels. The pixels may be arranged in the shape of a matrix”.
See Aygun Fig. 12, Fig. 14 see the red (R), green (G), and blue (B) subpixels, see “As shown in FIG. 12, the density of emissive sub-pixels is consistent across the active area AA. To accommodate a uniform emissive sub-pixel density across the display (while still having gate driver circuitry in the active area), the density of the thin-film transistor sub-pixels may be greater than the density of the emissive sub-pixels. The thin-film transistor sub-pixels therefore occupy a smaller footprint than the emissive sub-pixels. The thin-film transistor sub-pixels may be consolidated in a central portion of the active area, resulting in an area at the periphery of the active area where emissive sub-pixels can overlap gate driver circuitry” “FIG. 14 is a cross-sectional side view of the display shown in FIG. 12” “As shown in FIG. 14, conductive paths 76 allow for each emissive sub-pixel 62 to not necessarily vertically overlap the respective thin-film transistor sub-pixel 64 by which it is controlled. Some of the emissive sub-pixels are shifted laterally relative to their controlling thin-film transistor sub-pixel. Emissive sub-pixels may be shifted laterally relative to their controlling thin-film transistor sub-pixel either away from a center of the active area or towards the center of the active area”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kim to include that wherein the light emitting portions comprise a first light emitting portion, a second light emitting portion, and a third light emitting portion, which are configured to emit light of different wavelength regions from each other, wherein the first light emitting portion to the third light emitting portion constitute one light emitting unit, wherein a plurality of light emitting units each including the first to third light emitting portions are arranged in a first direction or in a second direction crossing the first direction.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is so that each pixel has the three colors Red, Green and Blue to display the color of choice in each pixel.
In regard to claim 7 Kim and Aygun as combined teaches wherein the circuit layer comprises [see Kim Fig. 4 each EL has a separate drive transistor] a first pixel driver electrically connected to the first light emitting portion, a second pixel driver electrically connected to the second light emitting portion, and a third pixel driver electrically connected to the third light emitting portion, wherein the first pixel driver to the third pixel driver constitute [see sombination, see RBG together form the desired color of the pixel] one driving unit, wherein a plurality of driving units each including the first pixel driver to the third pixel driver are arranged in the first direction [see Kim “display area DA may include a plurality of pixels. The pixels may be arranged in the shape of a matrix” see combination see Aygun Fig. 12, Fig. 14] or in the second direction.
In regard to claim 8 Kim and Aygun as combined teaches wherein a width of each of the driving units in the first direction is smaller [see this is true because, see combination the driving units are consolidated in a central portion of the active area, see a sample in Fig. 14 , see “The thin-film transistor sub-pixels therefore occupy a smaller footprint than the emissive sub-pixels” ] than a width of each of the light emitting units in the first direction.
Claim(s) 9, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Bok et al. (US 20210200366 A1) hereafter referred to as Bok
In regard to claim 9 Kim does not specifically teach wherein the extension wiring comprises a transparent conductive metal material.
See Kim teaches “fourth conductive layer 160 may include a connection electrode 161” “fourth conductive layer 160 may contain one or more metals selected from among molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth conductive layer 160 may be a single film or a multilayer film”.
See Bok teaches “In the top-emission structure where light exits from the emissive layer 172 toward the second light-emitting electrode 173, the first light-emitting electrode 171 may be made up of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al), or may be made up of a stack structure of aluminum and titanium (Ti/Al/Ti), a stack structure of aluminum and ITO (ITO/Al/ITO), an APC alloy and a stack structure of APC alloy and ITO (ITO/APC/ITO) in order to increase the reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd) and copper (Cu)” “third connection electrode PCC may be made up of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al), or may be made up of a stack structure of aluminum and titanium (Ti/Al/Ti), a stack structure of aluminum and ITO (ITO/Al/ITO), an APC alloy and a stack structure of an APC alloy and ITO (ITO/APC/ITO) in order to increase the reflectivity”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kim to include wherein the extension wiring comprises a transparent conductive metal material.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that ITO/Al/ITO is known to give good results for connectivity.
In regard to claim 10 Kim does not specifically teach wherein the driving connection part and the emission connection part each comprise a first layer including titanium, a second layer on an upper side of the first layer and including aluminum, and a third layer on an upper side of the second layer and including titanium, wherein all of the first through third layers are sequentially stacked.
See Kim teaches “third conductive layer 150 may contain one or more metals selected from among molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 150 may be a single film or a multilayer film” “third conductive layer 150 may include a first source/drain electrode 151 and a second source/drain electrode 152 of the transistor” “pixel electrode ANO is not limited thereto, but may have a stacked film structure where a high-work-function material layer such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), and indium oxide (In.sub.2O.sub.3) and a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) , lithium (Li), calcium (Ca), or mixtures thereof are stacked. The high-work-function material layer may be disposed above the reflective material layer, and thus, may be disposed close to an emission layer EL. The pixel electrode ANO may have a multilayer structure of ITO/Mg, ITO/MgF, ITO/Ag, and ITO/Ag/ITO, but the present disclosure is not limited thereto”.
See Bok teaches “In the top-emission structure where light exits from the emissive layer 172 toward the second light-emitting electrode 173, the first light-emitting electrode 171 may be made up of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al), or may be made up of a stack structure of aluminum and titanium (Ti/Al/Ti), a stack structure of aluminum and ITO (ITO/Al/ITO), an APC alloy and a stack structure of APC alloy and ITO (ITO/APC/ITO) in order to increase the reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd) and copper (Cu)” “third connection electrode PCC may be made up of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al), or may be made up of a stack structure of aluminum and titanium (Ti/Al/Ti), a stack structure of aluminum and ITO (ITO/Al/ITO), an APC alloy and a stack structure of an APC alloy and ITO (ITO/APC/ITO) in order to increase the reflectivity”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kim to include wherein the driving connection part and the emission connection part each comprise a first layer including titanium, a second layer on an upper side of the first layer and including aluminum, and a third layer on an upper side of the second layer and including titanium, wherein all of the first through third layers are sequentially stacked.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that a stack structure of aluminum and titanium (Ti/Al/Ti) is well known to give good results for connectivity and also good reflectance.
Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210143239 A1) hereafter referred to as Kim in view of Aygun et al. (US 11854490 B1) hereafter referred to as Aygun
In regard to claim 15 Kim teaches a display device separated into a display region [see “FIG. 1 is a plan view of a display device according to an embodiment” “FIG. 4 is a cross-sectional view showing an example section of a periphery of a bending area and a pixel according to an embodiment” “display area DA may include a plurality of pixels”] including [see that the display can be partitioned into 3 regions in X, Y directions to meet the claim limitation, wherein the first region is in the middle and the second region is away from the middle and the third region is at the edge] a first region, a second region, and a third region, which are arranged in a first direction, and a peripheral region [see Fig. 1 “display panel 100 may include a display area DA where a screen is displayed (e.g., a screen is configured to provide an image) and a non-display area NDA where a display is not realized (e.g., an image is not displayed)”] around the display region, the display device comprising:
a plurality of light emitting units [“The pixel electrode ANO, the emission layer EL, and the cathode electrode CAT may constitute an organic light emitting device” “display area DA may include a plurality of pixels”] in the first region to the third region, and each including a light emitting portion [see “emission layer EL” ];
a plurality of driving units in [see “silicon transistor region AR1”, see above the Examiner notes that simply saying driving units in the first region and the second region does not mean they are not in the third region as well, however in the interest of compact prosecution, there is also an additional 103 rejection below for that condition] the first region and the second region, and including a plurality of pixel drivers [see 152, 161, ANO “second source/drain electrode 152 may be connected to the second source/drain area 111b of the silicon semiconductor layer 111 through the second contact hole CNT2”] electrically connected to each of the light emitting portions; and
a plurality of connection wiring portions [see 152, 161, ANO] including an emission connection part [“pixel electrode ANO may be an anode electrode”] connected to each of the light emitting portions,
a driving connection part [“second source/drain electrode 152 may be connected to the second source/drain area 111b of the silicon semiconductor layer 111 through the second contact hole CNT2”] connected to each of the pixel drivers, and
an extension wiring [“the connection electrode 161 may be connected to the first and second source/drain electrodes 151 and 152 of the transistor disposed in the silicon semiconductor region AR1”] for connecting a corresponding emission connection part and the driving connection part,
wherein the driving connection part [see Fig. 4 see 152 does not overlap EL] does not overlap the light emitting portions
but does not state that each light emitting unit including a plurality of light emitting portions and (although not required) does not state that the driving units are not in the third region.
See Aygun Fig. 12, Fig. 14 see the red (R), green (G), and blue (B) subpixels, see “As shown in FIG. 12, the density of emissive sub-pixels is consistent across the active area AA. To accommodate a uniform emissive sub-pixel density across the display (while still having gate driver circuitry in the active area), the density of the thin-film transistor sub-pixels may be greater than the density of the emissive sub-pixels. The thin-film transistor sub-pixels therefore occupy a smaller footprint than the emissive sub-pixels. The thin-film transistor sub-pixels may be consolidated in a central portion of the active area, resulting in an area at the periphery of the active area where emissive sub-pixels can overlap gate driver circuitry” “FIG. 14 is a cross-sectional side view of the display shown in FIG. 12” “As shown in FIG. 14, conductive paths 76 allow for each emissive sub-pixel 62 to not necessarily vertically overlap the respective thin-film transistor sub-pixel 64 by which it is controlled. Some of the emissive sub-pixels are shifted laterally relative to their controlling thin-film transistor sub-pixel. Emissive sub-pixels may be shifted laterally relative to their controlling thin-film transistor sub-pixel either away from a center of the active area or towards the center of the active area”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Kim to include that each light emitting unit including a plurality of light emitting portions and that the driving units are not in the third region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is so that each pixel has the three colors Red, Green and Blue to display the color of choice in each pixel and so that the third region can be at the edge of the display and not have any driving units because all the driving units for first, second and third region are only in the first and second region so that the space in the third region can be used for gate driver circuitry in order to save area.
In regard to claim 16 Kim and Aygun as combined teaches wherein: the driving connection part electrically connected to the light emitting portions in the first region is in the first region [see these limitation are true because, see combination the driving units are consolidated in a central portion of the active area, see a sample in Fig. 14 ]; and the driving connection part electrically connected to the light emitting portions in the third region is in the second region.
In regard to claim 17 Kim and Aygun as combined teaches [see these limitation are true because, see combination the driving units are consolidated in a central portion of the active area, thus the wiring as you move toward the edge is increased, see a sample in Fig. 14 ] wherein the extension wiring for connecting the emission connection part connected to the light emitting portions in the third region and the driving connection part electrically connected to the emission connection part is longer than the extension wiring for connecting the emission connection part connected to the light emitting portions in the first region and the driving connection part electrically connected to the emission connection part.
In regard to claim 18 Kim and Aygun as combined teaches [see this is true because, see combination the driving units are consolidated in a central portion of the active area, thus the wiring as you move toward the edge is increased, see a sample in Fig. 14 ] wherein an extension wiring included in each of the connection wiring portions connected to the light emitting portions in the third region overlaps a plurality of light emitting portions.
In regard to claim 19 Kim and Aygun as combined teaches [see this is true because, see combination the driving units are consolidated in a central portion of the active area, see a sample in Fig. 14 , see “The thin-film transistor sub-pixels therefore occupy a smaller footprint than the emissive sub-pixels” ] wherein a width of each of the light emitting units in the first direction is larger than a width of each of the driving units in the first direction.
In regard to claim 20 Kim and Aygun as combined teaches wherein the pixel drivers each comprise a transistor [see Kim Fig. 4 “second source/drain electrode 152 may be connected to the second source/drain area 111b of the silicon semiconductor layer 111 through the second contact hole CNT2” see 152, 161, ANO] and an electrode pattern on the transistor and connected to the transistor, wherein the transistor includes: a semiconductor pattern including a source region, a drain region, and a channel region [“silicon semiconductor layer 111 may include a channel area 111c disposed in the thickness direction to overlap the first gate electrode 121 disposed thereabove and may also include a first source/drain area 111a and a second source/drain area 111b”] between the source region and the drain region; and a gate electrode [“first gate electrode 121”] on an upper side of the semiconductor pattern, wherein the driving connection part is electrically connected to [see Kim Fig. 4 “second source/drain electrode 152 may be connected to the second source/drain area 111b of the silicon semiconductor layer 111 through the second contact hole CNT2”] the drain region through the electrode pattern.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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