Prosecution Insights
Last updated: May 29, 2026
Application No. 18/585,179

Leakage Insensitive Switch Control for Bandgap Thermal Sensors in Core-MOS Nodes

Final Rejection §102
Filed
Feb 23, 2024
Examiner
CHEN, SIBIN
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
4 (Final)
87%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
889 granted / 1026 resolved
+18.6% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
25 currently pending
Career history
1041
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
67.0%
+27.0% vs TC avg
§102
27.7%
-12.3% vs TC avg
§112
3.6%
-36.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1026 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 16, 18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US 10,693,461). Regarding claim 16, fig. 1 of Chang discloses a method of reducing gate leakage current [e.g. via 140] comprising: receiving a digital control signal [SIGctrl]; based on the digital control signal, distributing a bias current through one or more of a plurality of transistors [M1A, M2A]; and coupling an operating transistor [P3] to an operating voltage node [e.g. voltage at gate of P3] and a ground transistor [N3] to a ground voltage node [VS], the coupling reducing a gate-to-source voltage of the one or more transistors [via 140], wherein the operating transistor includes a source/drain terminal connected to a gate terminal of the one or more transistors. Regarding claim 18, fig. 1 of Chang discloses wherein the operating transistor is a PMOS operating transistor having a gate terminal coupled to the operating voltage node. Regarding claim 20, fig. 1 of Chang discloses wherein the plurality of transistors are included in one of a plurality of current branches. Allowable Subject Matter Claims 1-4, 6, 7, 9, 10, 14, 15, and 21-25 are allowed. Claims 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim(s) 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIBIN CHEN/ Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Show 2 earlier events
Aug 12, 2025
Response Filed
Aug 20, 2025
Final Rejection mailed — §102
Oct 14, 2025
Response after Non-Final Action
Oct 30, 2025
Request for Continued Examination
Nov 06, 2025
Response after Non-Final Action
Jan 08, 2026
Non-Final Rejection mailed — §102
Apr 02, 2026
Response Filed
Apr 28, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12640727
ASYMMETRIC COMMON SOURCE INDUCTANCES TO REDUCE TURN-OFF OVERVOLTAGE IN MOSFETS
2y 1m to grant Granted May 26, 2026
Patent 12633913
GATE DRIVER
2y 2m to grant Granted May 19, 2026
Patent 12627293
SEMICONDUCTOR DEVICE
2y 2m to grant Granted May 12, 2026
Patent 12620978
USE OF PULSE WIDTH MODULATION TO GENERATE EXCITATION PULSES OFFSET FROM SAMPLING PULSES
1y 8m to grant Granted May 05, 2026
Patent 12615034
FET DRIVER CIRCUIT
2y 1m to grant Granted Apr 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

5-6
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+5.1%)
2y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1026 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month