Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/585,414 filed on 02/23/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election with traverse of Species I in the reply filed on 06/02/2026 is acknowledged.
Applicant’s traversal of the restriction requirement has been considered but is not persuasive.
As previously stated, the application is directed to at least two patentably distinct species:
Species I: a first embodiment outlined by Figs. 1-4, corresponding to claims 1-9 and 14; and
Species II: a second embodiment outlined by Figs. 5-9, corresponding to claims 10-13.
The species are mutually exclusive because Species I recites a first dummy chip having a flat top surface that is coplanar with adjacent structures, whereas Species II recites a first dummy chip comprising a plurality of trenches. These structural features define alternative and incompatible configurations and therefore are mutually exclusive.
Furthermore, the Examiner previously determined that the identified species are not obvious variants of one another based upon the current record.
Applicant’s assertion that there would be no serious burden on the Examiner is not persuasive. Examination of the elected and non-elected species would require different search strategies and search queries directed to materially different structural configurations associated with the respective species. Accordingly, examination of all species in a single application would impose a serious search and/or examination burden consistent with the requirements of MPEP § 808.01(a) and 808.02.
Accordingly, the traversal is not persuasive, and the restriction requirement under 35 U.S.C. § 121 is maintained and made final.
Applicant’s election of Species I, with traverse, has been acknowledged. Examination on the merits is directed to elected claims 1-9 and 14-20. Claims directed solely to the non-elected species are withdrawn from further consideration pursuant to 37 CFR 1.142(b).
The restriction requirement set forth in the Office Action mailed on 05/06/2026 is maintained and is hereby made final.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2018/0114782 Wang et al. (Wang).
Regarding independent claim 1, Wang discloses a package structure (Fig. 2E), comprising:
a lead frame (Fig. 2E: 110, a lead frame is considered equivalent to a circuit carrier 110);
a first flip-chip (120 and ¶0013) disposed over the lead frame (110);
a first dummy chip (330 or 130 and ¶0028 and ¶0015) affixed on the first flip-chip (120 by a non-conductive adhesive layer (340) to serve as heat dissipation (¶0028) paths for the first flip-chip (120); and
an encapsulant (Fig. 2E: 160) encapsulating the first flip-chip (120) and the first dummy chip (330).
Regarding claim 2, Wang discloses wherein the first flip-chip (120) is affixed on and electrically connected to the lead frame (110) through a plurality of bumps (122).
Regarding claim 3, Wang discloses wherein the bumps (122) are made of a single metal, an alloy, or a composite material (¶0013 such as copper).
Regarding claim 4, Wang discloses wherein the first dummy chip (330 or 130) has a flat top surface co-planar with a top surface of the encapsulant (Fig. 2D).
Regarding claim 14, Wang discloses wherein the encapsulant is made of epoxy, resin, moldable polymer, or a combination thereof (¶0020).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2018/0114782 Wang et al. (Wang) in view of US Pat # 6,114,761 to Mertol et al. (Mertol).
Regarding claim 5, Wang disclose all of the limitations of claim 1 from which this claim depends.
Wang fails to disclose wherein a width of the first dummy chip is greater than a width of the first flip-chip in a cross-sectional view.
Mertol discloses a heat spreader (Fig. 1A: 12) thermally attached to the upper surface of a flip chip (18), where the heat spreader has planar dimensions larger than the die to improve thermal dissipation. Although it uses the term “heat spreader” rather than “dummy chip,” it provides a strong rationale for a larger upper component used for thermal management.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the dummy chip of Wang with the disclosed width as taught by Mertol so as to increase the lateral dimensions of the dummy chip relative to the flip chip in order to increase thermal spreading area and improve heat dissipation performance (col. 5, lines 18-24).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2018/0114782 Wang et al. (Wang) in view of US Pub # 2016/0322330 to Lin et al. (Lin).
Regarding claim 6, Wang disclose all of the limitations of claim 1 from which this claim depends.
Wang discloses a semiconductor package including a lead frame, a first flip chip mounted to the lead frame, a dummy chip attached through a non-conductive adhesive layer, and an encapsulant surrounding the components (see the rejection of claim 1). However, Wang does not explicitly disclose that the width of the first dummy chip is less than the width of the first flip chip in a cross-sectional view.
Lin teaches dimensions smaller than the active dies (or flip-chip 102) (see Fig. 1B). In particular, Lin teaches embodiments in which flip-chip occupy a larger footprint while smaller dummy chip is employed (¶0014 and 0022) for stress balancing and coefficient of thermal expansion (CTE) control. Lin further explains that reducing the size of dummy chip (¶0025) allows improved filling of irregular spaces and reduction of wafer warpage.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the dummy chip of Wang with the disclosed width as taught by Lin in order to reduce package warpage, improve CTE matching, reduce unused silicon area and material consumption, and provide the desired mechanical support while minimizing package size and manufacturing cost (¶0011 and 0015).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2018/0114782 Wang et al. (Wang) in view of US Pub # 2015/0102485 to Kang et al. (Kang).
Regarding claim 7, Wang teaches the package structure of claim 1 including a first flip-chip mounted to a lead frame with a non-conductive adhesive layer disposed therebetween.
However, Wang does not explicitly disclose that the non-conductive adhesive layer comprises a non-conductive paste (NCP) or a non-conductive film (NCF) as recited.
Kim teaches that a non-conductive material layer used in semiconductor packages may comprise a non-conductive film (NCF) or a non-conductive paste (NCP) (¶0061 and 0115). In particular, Kim teaches that “the non-conductive material layer may be a non-conductive film (NCF) or a non-conductive paste (NCP) that is hardened” (¶0016). Kim further teaches the use of the NCF or NCP between semiconductor components connected through solder bumps in flip-chip package structures (¶0115).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to implement the non-conductive adhesive layer of Wang as the NCF or NCP taught by Kim because NCF and NCP were recognized and conventional non-conductive adhesive materials used in flip-chip and thermocompression bonding applications to provide mechanical attachment, insulation, underfill functionality, and improved package reliability (¶0180).
Regarding claim 8, Wang teaches the package structure of claim 1 including a non-conductive adhesive layer disposed in the flip-chip package. However, Wang does not explicitly disclose that the non-conductive adhesive layer has a thickness of 10 μm to 50 μm as recited.
Kim et al. teach the use of a non-conductive film (NCF) as the adhesive material in a flip-chip package and further disclose in paragraph [0074] that the NCF has a thickness within the claimed range of 10 μm to 50 μm. Therefore, Kim teaches the claimed thickness limitation.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to select the thickness of the non-conductive adhesive layer of Wang to be within the range taught by Kim (¶0074) because the thickness of the non-conductive adhesive layer affects bonding characteristics, package reliability, void formation, and proper filling of the space between the semiconductor chip and substrate during flip-chip assembly. A person of ordinary skill in the art would have been motivated to utilize the thickness taught by Kim in order to obtain the known benefits associated with reliable flip-chip bonding and improved package performance (¶0038). Thus, the modification merely involves the application of a known dimension for a known purpose in an analogous flip-chip packaging environment.
Regarding claim 9, Wang teaches the package structure of claim 1 including a first flip-chip electrically connected to a lead frame. However, Wang does not explicitly teach a second flip-chip disposed between the first flip-chip and the lead frame, wherein both the first flip-chip and the second flip-chip are electrically connected to the lead frame.
Kim, particularly (Figure 5), teaches a stacked semiconductor package (300) including a second flip-chip (such as a first semiconductor chip 320) between the first flip-chip (such as second semiconductor chip 340) and the lead frame (310), wherein both the first flip-chip and the second flip-chip are electrically connected to the lead frame (through connection pads 314, 316 and 326).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the package structure of Wang by incorporating the stacked flip-chip arrangement taught by Kim so as to provide a second flip-chip disposed between the first flip-chip and the lead frame while maintaining electrical connection of both chips to the lead frame because doing so would increase package integration density, reduce package footprint, improve utilization of vertical package space, and enable incorporation of additional functionality within a single semiconductor package.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2018/0114782 Wang et al. (Wang) in view of US Pub # 2025/0158001 to Chung et al. (Chung).
Regarding claim 15, Wang teaches the package structure of claim 1 including a first flip-chip 120 and a spacer 130 disposed on the first flip-chip, wherein paragraph [0015] teaches that the spacer 130 may serve as a dummy chip.
However, the primary reference does not explicitly teach a second dummy chip being juxtaposed to and spaced apart from the first dummy chip on the first flip-chip.
Chung teaches a semiconductor package including a plurality of dummy chips 340d. In particular, ¶0115 teaches that the plurality of dummy chips includes a first dummy chip (340_1) and a second dummy chip (340_2), and Figure 7 illustrates the first dummy chip (340_1) and second dummy chip (340_2) disposed adjacent to one another and separated by a space.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the package structure of the Wang by providing an additional dummy chip adjacent to and spaced apart from the first dummy chip as taught by Chung in order to discharging heat generated by the semiconductor chip (¶0082).
Allowable Subject Matter
Claims 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 16 recites:
“a plurality of heat sinks affixed on the first flip-chip and the second flip-chip.”
The considered prior art of record appears to fail to teach or render obvious the instant limitation in combination with all of the limitations of the independent claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2021/0407941 to Haba, US Pat # 6,593,662 to Pu et al., US Pub # 2025/0062245 to Chen et al., US Pub # 2003/0189245 to Fang.
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/MOHSEN AHMADI/Primary Examiner, Art Unit 2896
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