DETAILED ACTION
Election/Restrictions
1. Applicant’s election of Group I, claims 1 - 19 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claim Objections
2. Claims 4, 5, 13 are objected to because of the following informalities:
In claims 4, 5, 13, line 1, “the dielectric layer” should be changed to “the dielectric material” because it lacks of antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1, 4 – 6, 8, 9, 12 – 14, 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chae et al. (10439105).
With regard to claim 1, Chae et al. disclose a light emitting diode device (for example, see fig. 22C) comprising:
a mesa comprising semiconductor layers (110, 120, 130), the semiconductor layers (110, 120, 130) including an N-type layer (110; for example, see column 11, lines 62 – 64), an active layer (120), and a P-type layer (130), the mesa having a top surface and at least one sidewall, the at least one sidewall defining a trench (referred to as “T1” by examiner’s annotation shown in fig. 22C below) having a bottom surface;
an electrically conductive material (240) disposed in the trench (T1);
a p-type contact (a contact 140, is directly contact to p-type semiconductor 130, functioning as a p-type contact) on the top surface of the mesa (the mesa having semiconductor layers 110, 120, 130);
an n-contact (a current spreading layer 210, is directly contact to n-type semiconductor 110, functioning as a n-type contact) disposed between the electrically conductive material (240) in the trench (T1) and the semiconductor layers (110, 120, 130); and
an optical isolation layer (an insulating layer 220 functions as an optical isolation layer) disposed between the n-contact (210) and the electrically conductive material (240), the optical isolation layer (220) comprising a dielectric material (for example, see column 17, lines 64 – 67);
wherein the n-contact (210) and optical isolation layer (220) extend along an entire length of the at least one sidewall and bottom surface of the trench (T1).
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With regard to claim 4, Chae et al. disclose the dielectric material of the optical isolation layer (220) comprises silicon nitride (nitride insulation materials inherently including silicon nitride material; for example, see column 17, lines 64 – 67).
With regard to claim 5, Chae et al. disclose the dielectric material of the optical isolation layer (220) comprises silicon oxide (oxide insulation materials inherently including silicon nitride material; for example, see column 17, lines 64 – 67).
With regard to claim 6, Chae et al. disclose the electrically conductive material (240) comprises one or more of silver (Ag) and aluminum (for example, see column 18, lines 16 - 18).
With regard to claim 8, Chae et al. disclose the mesa further comprises a P-contact layer (a contact 140 or a portion of the layer 240, is contact to p-type semiconductor 130, functioning as a p-type contact).
With regard to claim 9, Chae et al. disclose a light emitting diode array (for example, see fig. 22C) comprising:
a plurality of mesas (the mesa having semiconductor layers 110, 120, 130) inherently using in pixels, each of the mesas comprising semiconductor layers (110, 120, 130), the semiconductor layers (110, 120, 130) including an N-type layer (110; for example, see column 11, lines 62 – 64), an active layer (120), and a P-type layer (130), each of the mesas having a top surface and sidewalls;
a plurality of trenches (referred to as “T1” by examiner’s annotation shown in fig. 22C below), each of the trenches (T1) disposed between each of the mesas, each of the trenches (T1) having a bottom surface and opposing side surfaces defining the sidewalls of the mesas;
an electrically conductive material (240) disposed in each of the trenches (T1);
a p-type contact (a contact 140, is directly contact to p-type semiconductor 130, functioning as a p-type contact) on the top surface of at least one mesa;
an n-contact (a current spreading layer 210, is directly contact to n-type semiconductor 110, functioning as a n-type contact) disposed along an entire length of the bottom surface of each of the trenches (T1) and along an entire length of the opposing side surfaces of each of the trenches (T1), the n-contact (210) disposed between the electrically conductive material (240) and the semiconductor layers (110, 120, 130); and
an optical isolation layer (an insulating layer 220 functions as an optical isolation layer) disposed along an entire length of the n-contact (210) in at least one trench (T1), the optical isolation layer (220) disposed between the electrically conductive material (240) and the n-contact (210) in the least one trench (T1), the optical isolation layer (220) comprising a dielectric material (for example, see column 17, lines 64 – 67).
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With regard to claim 12, Chae et al. disclose the dielectric material of the optical isolation layer (220) comprises silicon nitride (nitride insulation materials inherently including silicon nitride material; for example, see column 17, lines 64 – 67).
With regard to claim 13, Chae et al. disclose the dielectric material of the optical isolation layer (220) comprises silicon oxide (oxide insulation materials inherently including silicon nitride material; for example, see column 17, lines 64 – 67).
With regard to claim 14, Chae et al. disclose the electrically conductive material (240) comprises one or more of silver (Ag) and aluminum (for example, see column 18, lines 16 - 18).
With regard to claim 16, Chae et al. disclose the plurality of mesas inherently using in pixels are configured to be individually operable. (because the structure of Chae et al. is formed the same as that of applicant, thus the structure of Chae et al. has the same functions as the claimed invention.).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 2, 3, 10, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al. (10439105) in view of Heo (20240332451).
With regard to claims 2, 3, 10, 11, Chae et al. do not clearly disclose the n-contact comprises a transparent conductive oxide layer; wherein the transparent conductive oxide layer comprises zinc oxide.
However, Heo discloses the n-contact (24) comprises a transparent conductive oxide layer; wherein the transparent conductive oxide layer comprises zinc oxide (for example, see paragraph [0089], fig. 4A).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Chae et al.’s device to have the n-contact comprises a transparent conductive oxide layer; wherein the transparent conductive oxide layer comprises zinc oxide as taught by Heo in order to reduce the resistance of the electrode for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
7. Claims 7, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al. (10439105) in view of Lee et al. (10128306).
With regard to claims 7, 15, Chae et al. do not clearly disclose a light converting phosphor layer.
However, Heo discloses a light converting phosphor layer (43) (for example, see fig. 6).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Chae et al.’s device to have a light converting phosphor layer as taught by Heo in order to enhance a high light efficiency of the light emitting device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
8. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chae et al. (10439105) in view of Ikeda et al. (12183853).
With regard to claim 17, Chae et al. do not clearly disclose the light emitting diode (LED) array affixed to a device substrate by anode metallization bumps.
However, Heo discloses the light emitting diode (102, fig. 1B) array (array as shown in fig. 12) affixed to a device substrate (120) by anode metallization bumps (108, 112).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Chae et al.’s device to have the light emitting diode (LED) array affixed to a device substrate by anode metallization bumps as taught by Ikeda et al. in order to enhance a high light efficiency of the light emitting device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
9. Claims 18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al. (10439105) in view of Ikeda et al. (12183853) and further in view of Cui et al. (20260164793).
With regard to claims 18, 19, Chae et al. and Ikeda et al. do not clearly disclose the pixels emit a single color; wherein a first plurality of pixels is designed to emit a red color, a second plurality of pixels is designed to emit a blue color, and a third plurality of pixels is designed to emit a green color.
However, Cui et al. disclose the pixels (21) emit a single color (for example, see paragraph [0084]); wherein a first plurality of pixels is designed to emit a red color (each sub-pixel 21 may display a single color, such as red) a second plurality of pixels is designed to emit a blue color (each sub-pixel 21 may display a single color, such as blue), and a third plurality of pixels is designed to emit a green color. (each sub-pixel 21 may display a single color, such as blue).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Chae et al. and Ikeda et al.’s device to have the pixels emit a single color; wherein a first plurality of pixels is designed to emit a red color, a second plurality of pixels is designed to emit a blue color, and a third plurality of pixels is designed to emit a green color taught by Cui et al. in order to achieve display function of the light emitting device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights