DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Oath/Declaration
2. The oath/declaration filed on 02/23/2024 is acceptable.
Information Disclosure Statement
3. The office acknowledges receipt of the following items from the applicant:
Information Disclosure Statement (IDS) filed on 04/29/2024 and 08/01/2025.
Claim Objections
4. Claim 12 is objected to because of the following reason:
In claim 12, line 9, a phrase of “an electrically conductive material disposed in each of trenches;” should be deleted because the limitation is already recited in lines 11-12.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless --
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Armitage et al., hereafter “Armitage” (U.S. Patent No. 11,404,473 B2).
Regarding claim 1, Armitage discloses a light emitting diode (LED) device comprising:
at least one mesa (103/105/107) comprising semiconductor layers, the semiconductor layers including an n-type layer (116/126), an active layer (124), and a p-type layer (122), the at least one mesa (103/105/107) having a top surface and sidewalls, at least one sidewall defining a trench (111, Fig. 3) having a bottom surface;
a dielectric layer (130, Fig. 4) disposed on at least portions of the sidewalls;
an electrically conductive material (134) disposed in the trench (111) and in contact with the dielectric layer (130); and
a p-type contact (136, Fig. 8A) on the top surface of the mesa (103/105/107),
wherein the dielectric layer (130) extends between the semiconductor layers (116/124/122) and the electrically conductive material (134) along at least a portion of the trench (111) opposing sidewalls,
wherein at least a portion of the electrically conductive material (134) is in direct contact with at least a portion of the bottom surface of the trench (111) and/or at least a portion of the n-type layer (126), and
wherein the dielectric layer (130) optically isolates the trench (111) (Fig. 8B and col. 13, line 25-col. 14, line 34).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. Claims 2 and 10 are rejected under 35 U.S.C. 103(a) as being unpatentable over Armitage in view of Wildeson et al., hereafter “Wildeson” (U.S. Patent No. 10,804,429 B2).
Regarding claim 2, Armitage discloses the features of the claimed invention as discussed above, but does not disclose wherein the dielectric layer is further disposed on at least a portion of the bottom surface of the trench.
Wildeson, however, discloses wherein the dielectric layer (122) is further disposed on at least a portion of the bottom surface of the trench (112) (Figs. 1C-1E and col. 8, line 62).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Armitage to provide wherein the dielectric layer is further disposed on at least a portion of the bottom surface of the trench as taught by Wildeson for a purpose of increasing the withstand voltage for the light-emitting diode.
Regarding claim 10, Armitage discloses the features of the claimed invention as discussed above, but does not disclose further comprising a light converting phosphor layer.
Wildeson, however, discloses further comprising a light converting phosphor layer (206) (Fig. 2A and col. 14, line 39 and 56-58).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Armitage to provide further comprising a light converting phosphor layer as taught by Wildeson for a purpose of increasing efficiency and reducing heat degradation for the light-emitting diode.
7. Claims 6-7 are rejected under 35 U.S.C. 103(a) as being unpatentable over Armitage in view of Wildeson et al., hereafter “Wildeson’066” (U.S. Publicattion No. 2023/0155066 A1).
Regarding claim 6, Armitage discloses the features of the claimed invention as discussed above, but does not disclose wherein the dielectric layer comprises a material selected from the group consisting of silicon nitride (SiN), titanium oxide (TiOx), niobium oxide (NbOx), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum nitride (AlN), silicon oxide (SiOx), and hafnium-doped silicon dioxide (HfSiOx).
Wildeson’066, however, discloses wherein the dielectric layer (108) comprises a material selected from the group consisting of silicon nitride (SiN), titanium oxide (TiOx), niobium oxide (NbOx), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum nitride (AlN), silicon oxide (SiOx), and hafnium-doped silicon dioxide (HfSiOx) (Fig. 1C and para [0141]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to use the dielectric layer teaching of Wildeson’066 with Armitage because such material substitution or replacement would have been considered a mere substitution of art-recognized equivalent values, i.e. to reduce the leakage current. MPEP 2144.06.
Regarding claim 7, Armitage and Wildeson’066 (citations to Armitage unless otherwise noted) discloses wherein the dielectric layer comprises silicon oxide (Fig. 8B and col. 12, lines 5-6).
8. Claim 8 is rejected under 35 U.S.C. 103(a) as being unpatentable over Armitage and Wildeson’066 in view of Wildeson et al., hereafter “Wildeson’386” (U.S. Patent No. 11,476,386 B2).
Regarding claim 8, Armitage and Wildeson’066 discloses the features of the claimed invention as discussed above, but does not disclose wherein the dielectric layer has a thickness of at least about 0.2 microns
Wildeson’386, however, discloses wherein the dielectric layer (1024) has a thickness is larger than 100 or 500 or 1,000 nm (Fig. 17 and col. 21, lines 25-27).
However, the selection of the claimed process parameters would have been obvious to one having ordinary skill in the art before the effective filing date was made to provide the thickness of the dielectric layer is within the claimed range, since it is well settles that when the general conditions of a claim are discloses in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.ckness of at least about 0.2 microns
9. Claim 11 is rejected under 35 U.S.C. 103(a) as being unpatentable over Armitage and Wildeson’066 in view of Teo et al., hereafter “Teo” (U.S. Patent No. 11,705,534 B2).
Regarding claim 11, Armitage and Wildeson’066 discloses the features of the claimed invention as discussed above, but does not disclose the mesa further comprises a P-contact layer.
Teo, however, discloses the mesa further comprises a P-contact layer (205) (Fig. 2A).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Armitage to provide the mesa further comprises a P-contact layer as taught by Teo for a purpose of reducing power loss for the light-emitting diode.
10. Claim 12 is rejected under 35 U.S.C. 103(a) as being unpatentable over Armitage et al., hereafter “Armitage” (U.S. Patent No. 11,404,473 B2) in view of CHEN et al., hereafter “CHEN” (U.S. Publication No. 2020/0020739 A1).
Regarding claim 12, Armitage discloses a light emitting diode (LED) array comprising:
a plurality of mesas defining pixels (B/G/R), each of the mesas (103/105/107) comprising semiconductor layers, the semiconductor layers including an n-type layer (116/126), an active layer (124), and a p-type layer (122), each of the mesas (103/105/107) having a top surface and sidewalls;
a plurality of trenches (111), each of the trenches (111) disposed between each of the mesas (103/105/107), each of the trenches (1111) having a bottom surface and opposing side surfaces defining the sidewalls of the mesas (103/105/107);
a dielectric layer (130) disposed on at least portions of the sidewalls;
an electrically conductive material (134) disposed in the trench (111) and in contact with the dielectric layer (130); and
a p-type contact (136) on the top surface of at least one mesa (103/105/107),
wherein at least a portion of the electrically conductive material (134) is in direct contact with at least a portion of the bottom surface of at least one trench (111) and/or at least a portion of the n-type layer (116) in at least one trench (111), and
wherein the dielectric layer (130) optically isolates the trenches (111) (Fig. 8B and col. 13, line 25-col. 14, line 34.
Armitage discloses the features of the claimed invention as discussed above, but does not disclose at least one trench having a lower narrower portion and an upper wider portion, the upper wider portion further comprising opposing horizontal surfaces.
CHEN, however, discloses at least one trench (21) having a lower narrower portion (bottom portion with side S1) and an upper wider portion (upper portion with side S2), the upper wider portion (upper portion with side S2) further comprising opposing horizontal surfaces (204a/204b) (Fig. 4 and para [0048]-[0050]).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Armitage to provide at least one trench having a lower narrower portion and an upper wider portion, the upper wider portion further comprising opposing horizontal surfaces as taught by CHEN for a purpose of improving the reliability of filling the trench with insulating material and enhancing electrical isolation for the light-emitting device.
11. Claim 13 is rejected under 35 U.S.C. 103(a) as being unpatentable over Armitage and CHEN in view of Wildeson et al., hereafter “Wildeson” (U.S. Patent No. 10,804,429 B2).
Regarding claim 13, Armitage and CHEN discloses the features of the claimed invention as discussed above, but does not disclose wherein the dielectric layer is further disposed on at least a portion of the bottom surface of the trench.
Wildeson, however, discloses wherein the dielectric layer (122) is further disposed on at least a portion of the bottom surface of the trench (112) (Figs. 1C-1E and col. 8, line 62).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Armitage and CHEN to provide wherein the dielectric layer is further disposed on at least a portion of the bottom surface of the trench as taught by Wildeson for a purpose of increasing the withstand voltage for the light-emitting diode.
12. Claims 17-19 are rejected under 35 U.S.C. 103(a) as being unpatentable over Armitage and CHEN in view of LOPEZ T (WO-2024025753-A1).
Regarding claim 17, Armitage and CHEN disclose the features of the claimed invention as discussed above, but does not disclose a display comprising: the light emitting diode (LED) array according to claim 12 affixed to a device substrate by anode metallization bumps.
LOPEZ T, however, discloses a display comprising: the light emitting diode (LED) array according to claim 12 affixed to a device substrate by anode metallization bumps ((216) Fig. 3 and claim 15).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Armitage and CHEN to provide a display comprising: the light emitting diode (LED) array according to claim 12 affixed to a device substrate by anode metallization bumps as taught by LOPEZ T for a purpose of improving high-density electrical interconnects for the light-emitting diode.
Regarding claim 18, Armitage, CHEN and LOPEZ T (citations to Armitage unless otherwise noted) discloses wherein the pixels emit a single color (B/R/G) (Fig. 8B).
Regarding claim 19, Armitage, CHEN and LOPEZ T (citations to Armitage unless otherwise noted) discloses wherein a first plurality of pixels is designed to emit a red color ®, a second plurality of pixels is designed to emit a blue color (B), and a third plurality of pixels is designed to emit a green color (G) (Fig. 8B).
Allowable Subject Matter
13. The following is a statement of reason for the indication of allowable subject matter:
Claims 3-5 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Arts
14. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Robin (U.S. Patent No. 12.176,379 B2) discloses a light emitting diode (LED) device comprising:
at least one mesa (111/112/113) comprising semiconductor layers, the semiconductor layers including an n-type layer (see Fig. 101b/101a in Fig. 1), an active layer (104/106/108), and a p-type layer (see Fig. 101b/101a in Fig. 1), the at least one mesa (111/112/113) having a top surface and sidewalls, at least one sidewall defining a trench (14) having a bottom surface;
a dielectric layer (15) disposed on at least portions of the sidewalls;
an electrically conductive material (132) disposed in the trench (14) and in contact with the dielectric layer (15); and
wherein the dielectric layer (15) extends between the semiconductor layers and the electrically conductive material (132) along at least a portion of the trench (14) opposing sidewalls,
wherein at least a portion of the electrically conductive material (132) is in direct contact with at least a portion of the bottom surface of the trench (14) and/or at least a portion of the n-type layer (see Fig. 1), and
wherein the dielectric layer (15) optically isolates the trench (14) (Fig. 9).
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUC T DANG/Primary Examiner, Art Unit 2897
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