DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites “A semiconductor package, comprising: … a first substrate having a first surface and a second surface opposite to the first surface, … first bonding pads provided on the first surface of the first substrate … a polishing stop layer pattern provided on the second surface of the first substrate … second bonding pads provided on the polishing stop layer pattern”. Here, first bonding pads and second bonding pads are on opposite side of the first substrate. It is not clear how the semiconductor package of claim 11 can have “wherein the first bonding pads and the second bonding pads are directly bonded to each other” as recited in lines 17-18 of claim 11. For examination purposes, the limitation is considered as: wherein the first bonding pads (125) and the third bonding pads (225) are directly bonded to each other, as depicted in FIG. 2 and in related text in the Specification of the instant Application.
Claim 18 recites the limitation "the filling layer pattern" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites the limitation "the first surface" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites the limitation "the first surface" in line 18. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 2020/0381397).
Regarding claim 1, Yu discloses, in FIG. 9 and in related text, a semiconductor package, comprising:
a first semiconductor chip including a first substrate (120), a plurality of through electrodes (126) penetrating the first substrate, first bonding pads (142) provided on a first surface (upper surface in FIG. 9) of the first substrate and electrically connected to the plurality of through electrodes, a first passivation layer (134) provided on the first surface of the first substrate and exposing at least portions of the first bonding pads, a polishing stop layer pattern (layer immediately below first substrate 120 in FIG. 9; see 154 in FIG. 7) provided on a second surface (lower surface in FIG. 9) opposite to the first surface of the first substrate and exposing end portions of the plurality of through electrodes, and second bonding pads (160) provided on the polishing stop layer pattern and electrically connected to the plurality of through electrodes; and
a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip including a second substrate (220), third bonding pads (242) provided on a first surface (lower surface in FIG. 9) of the second substrate, and a second passivation layer (234) provided on the first surface of the second substrate and exposing at least portions of the third bonding pads,
wherein the first bonding pads (142) and the third bonding pads (242) are directly bonded to each other (see Yu, [0013], [0019]-[0021], [0030], [0032]).
Regarding claim 2, Yu discloses the package of claim 1.
Yu discloses wherein the first passivation layer (134) and the second passivation layer (234) are directly bonded to each other (see Yu, [0021]).
Regarding claim 3, Yu discloses the package of claim 1.
Yu discloses wherein the end portions of the plurality of through electrodes (126) protrude from the second surface (lower surface in FIG. 9) of the first substrate (120), and the polishing stop layer pattern (layer immediately below first substrate 120 in FIG. 9; see 154 in FIG. 7) covers side walls of the end portions of the plurality of through electrodes that protrude from the second surface of the first substrate (see Yu, FIG. 9).
Regarding claim 4, Yu discloses the package of claim 1.
Yu discloses wherein a lower surface (upper surface in FIG. 7) of the polishing stop layer pattern (154 in FIG. 7) and lower surfaces (upper surface in FIG. 7) of the end portions of the plurality of through electrodes (126) are positioned on a same plane (see Yu, FIG. 7, [0030]).
Regarding claim 5, Yu discloses the package of claim 1.
Yu discloses wherein the polishing stop layer pattern (154) includes silicon nitride (see Yu, [0030]).
Regarding claim 7, Yu discloses the package of claim 1.
Yu discloses wherein the polishing stop layer pattern (154) covers the entire second surface (upper surface in FIG. 7) of the first substrate (120) (see Yu, FIG. 7).
Regarding claims 8-9, Yu discloses the package of claim 1.
Yu discloses wherein the first semiconductor chip further comprises a filling layer pattern (148, 150) that covers outer surfaces of the first substrate (120) and the polishing stop layer pattern (154), wherein the filling layer pattern includes silicon oxide (see Yu, FIG. 7, [0024]-[0025]).
Claims 11-14 and 16-18, as so far as understood, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 2020/0381397).
Regarding claim 11, Yu discloses, in FIG. 9 and in related text, a semiconductor package, comprising:
a first substrate structure including a first substrate (120) having a first surface (upper surface in FIG. 9) and a second surface (lower surface in FIG. 9) opposite to the first surface, a plurality of through electrodes (126) penetrating the first substrate and having end portions that protrude from the second surface, first bonding pads (142) provided on the first surface of the first substrate and electrically connected to the plurality of through electrodes, a first passivation layer (134) provided on the first surface of the first substrate and exposing at least portions of the first bonding pads, a polishing stop layer pattern (layer immediately below first substrate 120 in FIG. 9; see 154 in FIG. 7) provided on the second surface of the first substrate and exposing the protruding end portions of the plurality of through electrodes, and second bonding pads (160) provided on the polishing stop layer pattern and electrically connected to the plurality of through electrodes; and
a second substrate structure including a second substrate (220), third bonding pads (242) provided on a first surface (lower surface in FIG. 9) of the second substrate, and a second passivation layer (234) provided on the first surface of the second substrate and exposing at least portions of the third bonding pads, wherein the second substrate structure is stacked on the first substrate structure such that the third bonding pads face the first bonding pads,
wherein the first bonding pads (142) and the second bonding pads (note: third ponding pads 242) are directly bonded to each other, and
wherein the first passivation layer (134) and the second passivation layer (234) are directly bonded to each other (see Yu, [0013], [0019]-[0021], [0030], [0032]).
Regarding claim 12, Yu discloses the package of claim 11.
Yu discloses wherein the polishing stop layer pattern (154) covers sidewalls of the protruding end portions of the plurality of through electrodes (126) (see Yu, FIG. 7).
Regarding claim 13, Yu discloses the package of claim 11.
Yu discloses wherein a lower surface (upper surface in FIG. 7) of the polishing stop layer pattern (154) and lower surfaces (upper surface in FIG. 7) of the protruding end portions of the plurality of through electrodes (126) are positioned on a same plane (see Yu, FIG. 7, [0030]).
Regarding claim 14, Yu discloses the package of claim 11.
Yu discloses wherein the polishing stop layer pattern (154) includes silicon nitride (see Yu, [0030]).
Regarding claim 16, Yu discloses the package of claim 11.
Yu discloses wherein the polishing stop layer pattern (154) covers the entire second surface of the first substrate (120) (see Yu, FIG. 7).
Regarding claim 17, Yu discloses the package of claim 11.
Yu discloses wherein the first substrate structure further comprises a filling layer pattern (148, 150) covering outer surfaces of the first substrate (120) and the polishing stop layer pattern (154) (see Yu, FIG. 7, [0024]-[0025]).
Regarding claim 18, Yu discloses the package of claim 11.
Yu discloses wherein the filling layer pattern (148, 150) includes silicon oxide (see Yu, [0024]-[0025]).
Claim 20, as so far as understood, is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2020/0161277).
Regarding claim 20, Lee discloses, in FIG. 1 and in related text, a semiconductor package, comprising:
a package substrate (500);
a first semiconductor chip (100) stacked on the package substrate; and
a second semiconductor chip (200) stacked on the first semiconductor chip,
wherein the first semiconductor chip (100) includes:
a first substrate (110);
a plurality of penetration electrodes (162) penetrating the first substrate;
first bonding pads (182) provided on the first surface (upper surface) of the first substrate;
a first passivation layer (180) provided on the first surface of the first substrate and exposing the first bonding pads;
a polishing stop layer pattern (130) provided on a second surface (lower surface) of the first substrate opposite to the first surface and exposing end portions of the plurality of through electrodes;
second bonding pads (136) provided on the polishing stop layer pattern; and
conductive bumps (600) respectively provided on the second bonding pads,
wherein the second semiconductor chip (200) includes:
a second substrate (210);
third bonding pads (236) provided on the first surface (lower surface) of the second substrate; and
a second passivation layer (230) provided on the first surface of the second substrate and exposing at least portions of the third bonding pads, and
wherein the first bonding pads (182) and the third bonding pads (236) are directly bonded to each other (see Lee, [0025], [0030], [0044]-[0046]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yu.
Regarding claim 6, Yu discloses the package of claim 1.
Yu discloses the polishing stop layer pattern (154) has non-zero thickness (see Yu, [0030]). Yu does not explicitly disclose wherein the polishing stop layer pattern has a thickness within a range of 0.1 μm to 1 μm.
Here, the thickness of the polishing stop layer pattern contributes to the overall thickness of the package. And the overall thickness of the package affects signal transmission performance of the package (see Yu, [0061]). In other words, the thickness of the polishing stop layer pattern is a result effective variable for varying.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to have the claimed range/value through routine experimentation and optimization. Also, applicant has not disclosed that the claimed range is for a particular unobvious purpose, produces an unexpected result, or otherwise critical. See MPEP § 2144.05.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yu.
Regarding claim 15, Yu discloses the package of claim 11.
Yu discloses the polishing stop layer pattern (154) has non-zero thickness (see Yu, [0030]). Yu does not explicitly disclose wherein the polishing stop layer pattern has a thickness within a range of 0.1 μm to 1 μm.
Here, the thickness of the polishing stop layer pattern contributes to the overall thickness of the package. And the overall thickness of the package affects signal transmission performance of the package (see Yu, [0061]). In other words, the thickness of the polishing stop layer pattern is a result effective variable for varying.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to have the claimed range/value through routine experimentation and optimization. Also, applicant has not disclosed that the claimed range is for a particular unobvious purpose, produces an unexpected result, or otherwise critical. See MPEP § 2144.05.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2022/0077116).
Regarding claim 1, Park discloses, in FIGS. 1-2 and in related text, a semiconductor package, comprising:
a first semiconductor chip (100) including a first substrate (110), through electrode (120) penetrating the first substrate, first bonding pads (195A) provided on a first surface (upper surface) of the first substrate and electrically connected to the through electrode, a first passivation layer (190) provided on the first surface of the first substrate and exposing at least portions of the first bonding pads, a polishing stop layer pattern (165) provided on a second surface (lower surface) opposite to the first surface of the first substrate and exposing end portions of the through electrode, and second bonding pad (170A) provided on the polishing stop layer pattern and electrically connected to the through electrode; and
a second semiconductor chip (200) stacked on the first semiconductor chip, the second semiconductor chip including a second substrate (210), third bonding pads (255A) provided on a first surface (lower surface) of the second substrate, and a second passivation layer (250) provided on the first surface of the second substrate and exposing at least portions of the third bonding pads,
wherein the first bonding pads (195A) and the third bonding pads (255A) are directly bonded to each other (see Park, [0024]-[0025], [0044]-[0046], [0074]).
Park does not explicitly disclose a plurality of through electrodes; second bonding pads.
However, the limitations are considered as duplication of parts and would have been found obvious. [T]he court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also, MPEP § 2144.04.
Regarding claim 10, Park teaches the package of claim 1.
Park discloses wherein the first semiconductor chip further comprises conductive bump (50) respectively provided on the second bonding pad (170A) (see Park, FIG. 2, [0030], [0044]).
Park teaches the second bonding pads (see discussion on claim 1 above). Thus Park also teaches conductive bumps that are respectively provided on the second bonding pads, as the limitation is mere duplication of parts.
Claims 11 and 19, as so far as understood, are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2022/0077116).
Regarding claim 11, Park discloses, in FIGS. 1-2 and in related text, a semiconductor package, comprising:
a first substrate structure (100) including a first substrate (110) having a first surface (upper surface) and a second surface (lower surface) opposite to the first surface, a through electrode (120) penetrating the first substrate and having end portion that protrude from the second surface, first bonding pads (195A) provided on the first surface of the first substrate and electrically connected to the through electrode, a first passivation layer (190) provided on the first surface of the first substrate and exposing at least portions of the first bonding pads, a polishing stop layer pattern (165) provided on the second surface of the first substrate and exposing the protruding end portion of the through electrode, and second bonding pad (170A) provided on the polishing stop layer pattern and electrically connected to the through electrode; and
a second substrate structure (200) including a second substrate (210), third bonding pads (255A) provided on a first surface (lower surface) of the second substrate, and a second passivation layer (250) provided on the first surface of the second substrate and exposing at least portions of the third bonding pads, wherein the second substrate structure is stacked on the first substrate structure such that the third bonding pads face the first bonding pads,
wherein the first bonding pads (190A) and the second bonding pads (note: third bonding pads 255A) are directly bonded to each other, and
wherein the first passivation layer (190) and the second passivation layer (250) are directly bonded to each other (see Park, [0024]-[0025], [0044]-[0046], [0074]).
Park does not explicitly disclose a plurality of through electrodes; protruding end portions; second bonding pads.
However, the limitations are considered as duplication of parts and would have been found obvious. [T]he court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also, MPEP § 2144.04.
Regarding claim 19, Park teaches the package of claim 1.
Park discloses wherein the first substrate further includes conductive bump (50) respectively provided on the second bonding pad (170A) (see Park, FIG. 2, [0030], [0044]).
Park teaches the second bonding pads (see discussion on claim 11 above). Thus Park teaches conductive bumps that are respectively provided on the second bonding pads, as the limitation is mere duplication of parts.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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