Prosecution Insights
Last updated: October 22, 2026
Application No. 18/585,539

SEMICONDUCTOR PROCESSING FOR FORMING ISOLATION STRUCTURE IN SEMICONDUCTOR SUBSTRATE

Non-Final OA §102§103§112
Filed
Feb 23, 2024
Examiner
AU, BAC H
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
690 granted / 851 resolved
+13.1% vs TC avg
Moderate +11% lift
Without
With
+10.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
15 currently pending
Career history
871
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
28.0%
-12.0% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 851 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I, encompassing claims 1-9, 16, and 17, in the reply filed on July 22, 2026, is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 16, the limitation “the nitride layer having an etch rate by hydrofluoric acid in a range from 20 Angstroms per minute (Å/m) to 30 Å/m” in lines 3-4 appears to claim a physical characteristic of the nitride layer, wherein the characteristic seems to be dependent upon the parameters of the etching process. It is also not clear what is required by the limitation. As this limitation is not an actual process step of the claimed method, it will be interpreted as the nitride layer is able to be etched by hydrofluoric acid in a range from 20 Angstroms per minute (Å/m) to 30 Å/m. Claim 17 is rejected due to its dependency. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moon (U.S. Pat. 5719085). Regarding claims 1-3, Moon [Figs.3A-K] discloses a method, comprising: forming a first dielectric layer [302] over a semiconductor substrate [300]; forming a second dielectric layer [304] over the first dielectric layer; forming a recess [310] through the second dielectric layer and the first dielectric layer into the semiconductor substrate [Fig.3B]; cleaning the recess including using an etchant, a ratio of an etch rate of the first dielectric layer by the etchant to an etch rate of the second dielectric layer by the etchant being in a range from 0.10 to 4 [Figs.3B-C] [Col.4 line 66 – col.5 line 27]; and filling the recess in the semiconductor substrate with a dielectric material [326] [Fig.3K]; wherein: the first dielectric layer [302] is silicon oxide; and the second dielectric layer [304] is silicon nitride [Col.3 line 58 – col.4 line 28]; wherein the etchant includes hydrofluoric acid [Col.4 line 66 – col.5 line 27]. Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo (U.S. Pat. 5989975). Regarding claims 1 and 4, Kuo [Figs.3-4] discloses a method, comprising: forming a first dielectric layer [21] over a semiconductor substrate [20]; forming a second dielectric layer [22] over the first dielectric layer; forming a recess [24] through the second dielectric layer and the first dielectric layer into the semiconductor substrate [Fig.3B]; cleaning the recess including using an etchant, a ratio of an etch rate of the first dielectric layer by the etchant to an etch rate of the second dielectric layer by the etchant being in a range from 0.10 to 4 [Figs.3B-C,4] [Col.3 line 55 – col.4 line 7]; and filling the recess in the semiconductor substrate with a dielectric material [Col.4 lines 14-17]; wherein the etchant laterally pulls back the second dielectric layer [22] and the first dielectric layer [21], a sidewall of the first dielectric layer being under the second dielectric layer or aligned [Fig.4] to a sidewall of the second dielectric layer after cleaning the recess [Figs.3B-C,4] [Col.3 line 55 – col.4 line 7]. Claim(s) 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramkumar (U.S. Pat. 6838392). Regarding claims 16-17, Ramkumar [Figs.6-12] discloses a method, comprising: forming an oxide layer [26] over a semiconductor substrate; forming a nitride layer [28] over the oxide layer, the nitride layer having an etch rate by hydrofluoric acid in a range from 20 Angstroms per minute (Å/m) to 30 Å/m [Fig.6; the nitride layer [28] is able to be etched by hydrofluoric acid in a range from 20 Angstroms per minute (Å/m) to 30 Å/m]; forming a trench [30] through the nitride layer and the oxide layer into the semiconductor substrate [Fig.8]; cleaning the trench including using hydrofluoric acid [Fig.9] [Col.3 line 46 – col.4 line 2; col.5 lines 24-38]; and filling the trench in the semiconductor substrate with a dielectric material [40] [Fig.12]; wherein cleaning the trench including using hydrofluoric acid pulls back a sidewall of the nitride layer from a boundary of the trench a distance in a range from 50 Å to 200 Å [Fig.9] [Col.3 line 46 – col.4 line 2; col.5 lines 24-38]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (U.S. Pat. 5989975). Regarding claim 5, Kuo [Fig.3D] discloses the method further comprising: forming an oxide layer [26] after cleaning the recess and before filling the recess. Kuo fails to explicitly disclose wherein the second dielectric layer shrinks as a result of forming the oxide layer. However, oxide layer [26] is formed using a high temperature oxidation method [Col.4 lines 8-10]. It would appear obvious that the second dielectric layer [22] shrinks as a result of forming the oxide layer [as result of the high temperature exposure during the oxidation process]. It would have been obvious to include wherein the second dielectric layer shrinks as a result of forming the oxide layer, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon (U.S. Pat. 5719085) in view of Luo (U.S. Pub. 2004/0086640). Regarding claims 6-7, Moon fails to explicitly disclose the claimed deposition process and the annealing. However, Luo [Para.7] discloses a method wherein forming the second dielectric layer includes depositing the second dielectric layer in a deposition process, the deposition process including flowing hexachlorodisilane gas and ammonia gas [Para.7]; wherein forming the second dielectric layer includes annealing the second dielectric layer after depositing the second dielectric layer [Para.88]. It would have been obvious to include wherein the deposition process including flowing hexachlorodisilane gas and ammonia gas and annealing the second dielectric layer after depositing the second dielectric layer to provide improved etch properties [Luo; Para.90], and since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon (U.S. Pat. 5719085) in view of Luo (U.S. Pub. 2004/0086640), and further in view of Saly (U.S. Pub. 2017/0114459). Regarding claims 8-9, Moon and Luo [Discussed above in the treatment of claims 6-7] discloses the method wherein forming the second dielectric layer includes depositing the second dielectric layer in a deposition process, the deposition process including flowing silane gas and ammonia gas; wherein forming the second dielectric layer includes annealing the second dielectric layer after depositing the second dielectric layer. Moon and Luo fail to explicitly disclose the deposition process including flowing silane gas and ammonia gas with a process temperature less than 375 °C. However, Saly [Para.92] discloses wherein forming the second dielectric layer includes depositing the second dielectric layer in a deposition process, the deposition process including flowing silane gas and ammonia gas with a process temperature less than 375 °C [Paras.87,92]. It would have been obvious to provide the claimed process temperature, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BAC H AU/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Feb 23, 2024
Application Filed
Oct 14, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
92%
With Interview (+10.9%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 851 resolved cases by this examiner. Grant probability derived from career allowance rate.

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