DETAILED ACTION
This correspondence is in response to the communications received June 17, 2026. Claims 1-3, 8-11, 13, 14 and 19-21 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 4-7, 12, 15-18 and 22-27 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species I and III, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 17, 2026. Applicant’s election without traverse of Species II (claims 1-3, 8-11, 13, 14 and 19-21) in the reply filed on June 17, 2026 is acknowledged.
Relevant Prior Art
Uzoh et al. (US 11,652,083) Figs. 5(A)-5(C), shown below.
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Wang et al. (US 12,581,994) Fig. 5, first part, shown below.
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Dubey et al. (US 2016/0233175) Figs. 12 and 13, shown below.
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Lee et al. (US 11,557,559) Figs. 1A, 3G, shown below.
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Wang et al. (US 10,763,223) Fig. 2, shown below.
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Eun (US 2008/0036082) Fig. 16B, shown below.
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Wu et al. (US 2024/0096848) Fig. 11, shown below.
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Cheng et al. (US 2015/0228557) Fig. 1F, shown below.
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 4B and 10D (Fig. 1B is included to utilize a drawing with fully identified features, however it is noted that Fig. 1B is not fully representative of the elected embodiment of Species II), an integrated circuit structure comprising:
an integrated circuit (IC) die (110, ¶ 0040) including a first bonding surface (112, ¶ 0040), a first lateral edge (114, ¶ 0040) and a first edge recess (116A, ¶ 0040) in the first bonding surface (112);
an electronic component (130, ¶ 0040) including a second bonding surface (132, ¶ 0040) bonded directly to the first bonding surface (132 meets 112); and
a molding compound (150, ¶ 0051) that spans across the electronic component (110) and the first lateral edge (114), and fills the first edge recess (150 fills 116A).
Regarding claim 13, the Applicant discloses in Fig. 4B and 10D, an integrated circuit die comprising:
a first planar bonding surface (112), a first lateral edge (114) and a first edge recess (116A) in the first planar bonding surface (in 112);
wherein the first edge recess (116A) is characterized by a first width (w1) that extends from the first lateral edge (114) to a first interior edge (117, ¶ 0040), and
a first depth (d1) that extends from the first planar bonding surface (112) to a first roof (117).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10, 13, 14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou (US 2024/0047424).
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Regarding claim 1, the prior art of Zhou discloses in Figs. 1A (utilized as a completely labeled version of what is shown in Fig. 8), 3 (Fig. 3 is similar to Fig. 1, but with lower side recesses, see ¶ 0028) and Fig. 8 (annotated by Examiner), an integrated circuit structure (“The semiconductor die 100 can further include one or more circuit elements 104 (shown schematically), such as wires, traces, interconnects, transistors, and/or the like formed in (e.g., embedded in) and/or on the substrate 102.”, ¶ 0018, and, “integrated circuit elements can be located in the substrate 102 beneath the metal traces. The circuit elements 104 can include integrated memory circuitry and/or logic circuitry …”, ¶ 0018) comprising:
an integrated circuit (IC) die (“The semiconductor die 100 can further include one or more circuit elements 104 (shown schematically), such as wires, traces, interconnects, transistors, and/or the like formed in (e.g., embedded in) and/or on the substrate 102.”, ¶ 0018, and, “integrated circuit elements can be located in the substrate 102 beneath the metal traces. The circuit elements 104 can include integrated memory circuitry and/or logic circuitry …”, ¶ 0018. See 11b in Fig. 8, where Examiner has annotated this particular die as ‘integrated circuit die’ and “semiconductor die 100b”, ¶ 0031) including a first bonding surface (Fig. 8’s 100b is annotated to show the ‘first bonding surface’, and Fig. 1A shows the lower bonding surface as the lower surface of “first bonding layer or structure 110”, ¶ 0019, this is Fig. 3’s lower surface of “first bonding structure 110”, ¶ 0031), a first lateral edge (Fig. 8’s 100b is annotated to show the ‘first lateral edge’) and a first edge recess (“recess 342”, ¶ 0028 associated with 100b) in the first bonding surface (342 is a recess at least in the identified annotated, ‘first bonding surface’);
an electronic component (100a, “semiconductor dies 100 (identified individually as first through fourth semiconductor dies 100a-d, respectively)”, ¶ 0029, and annotated by Examiner as ‘electronic component’) including a second bonding surface (Examiner annotated ‘second bonding surface’) bonded directly to the first bonding surface (Examiner annotated ‘first bonding surface’ and “second bonding surface” are shown in direct contact with each other, showing a “direct bond”); and
a molding compound (“mold material 854”, ¶ 0053) that spans across the electronic component (854 laterally is wider, and covers 100b) and the first lateral edge (854 covers annotated ‘first lateral edge’), and fills the first edge recess (854 fills the 342 associated with 100b).
Although Zhou does not explicitly state that Figs. 1 and 3 are variations of each other, it is clear that Fig. 3 shares many of the same labels as Fig. 1, however Fig. 3 has lower surface recesses, and in ¶ 0011, “a plurality of the semiconductor dies shown in FIG. 3 in accordance with additional embodiments of the present technology.”
So it would have been obvious to one of ordinary skill in the art that the “integrated circuit” 104 described for Fig. 1 in ¶ 0018, would also share that 104 in Fig. 3 is an “integrated circuit”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “an integrated circuit (IC) die”, as disclosed by Fig. 1 of Zhou in the system of Figs. 3 and 8 of Zhou, for the purpose of utilizing a configuration of circuitry integrated in large scale on a diminutively sized semiconductor die, which allows for high device density per unit area, and thus increasing functionality. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Zhou discloses the integrated circuit structure of claim 1, wherein the first edge recess is characterized by a first width that extends from the first lateral edge to a first interior edge, and a first depth that extends from the first bonding surface to a first roof (In Figs. 1, 3 and 8, Zhou discloses, “In some embodiments, the width W can be greater than the length L of the recesses 120, 122”, ¶ 0039).
Regarding claim 3, the prior art of Zhou discloses the integrated circuit structure of claim 2, wherein the first width is a greater distance than the first depth (In Figs. 1, 3 and 8, Zhou discloses, “In some embodiments, the width W can be greater than the length L of the recesses 120, 122”, ¶ 0039).
Regarding claim 10, the prior art of Zhou discloses the integrated circuit structure of claim 1, wherein the first bonding surface is hybrid bonded with the second bonding surface (Zhou discloses in Fig. 8, wherein the annotated ‘first bonding surface’ is directly bonded to the ‘second bonding surface’, which includes both insulation material surface and conductive feature surfaces bonded to insulation and conductive surfaces, “passivation materials 111, 115 surround and electrically insulate the conductive contacts 113, 117”, ¶ 0019. So ‘second bonding surface’ of 100a would bond to the ‘first bonding surface’ of 100b, the hybrid bond meaning that the insulators bond to the insulators, and the conductors bond to the conductors).
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Regarding claim 13, the prior art of Zhou discloses in Figs. 1A (utilized as a completely labeled version of what is shown in Fig. 8), 3 (Fig. 3 is similar to Fig. 1, but with lower side recesses, see ¶ 0028) and Fig. 8 (annotated by Examiner), an integrated circuit structure (“The semiconductor die 100 can further include one or more circuit elements 104 (shown schematically), such as wires, traces, interconnects, transistors, and/or the like formed in (e.g., embedded in) and/or on the substrate 102.”, ¶ 0018, and, “integrated circuit elements can be located in the substrate 102 beneath the metal traces. The circuit elements 104 can include integrated memory circuitry and/or logic circuitry …”, ¶ 0018) comprising:
a first planar bonding surface (Fig. 8’s 100b is annotated to show the ‘first bonding surface’, and Fig. 1A shows the lower bonding surface as the lower surface of “first bonding layer or structure 110”, ¶ 0019, this is Fig. 3’s lower surface of “first bonding structure 110”, ¶ 0031), a first lateral edge (Fig. 8’s 100b is annotated to show the ‘first lateral edge’) and a first edge recess (“recess 342”, ¶ 0028, associated with “semiconductor die 100b”, ¶ 0031, which is also annotated as ‘integrated circuit die’) in the first planar bonding surface (lower surface of 110 and Examiner annotated ‘first bonding surface’ in annotated Fig. 8);
wherein the first edge recess (342) is characterized by a first width that extends from the first lateral edge to a first interior edge (342 has a width in the lateral direction, extending from annotated ‘first lateral edge’ in Fig. 8 to vertical surface of 342), and
a first depth that extends from the first planar bonding surface to a first roof (Fig. 8, a first depth that extends from annotated ‘first bonding surface’ to the horizontal and downward facing surface of 342).
Although Zhou does not explicitly state that Figs. 1 and 3 are variations of each other, it is clear that Fig. 3 shares many of the same labels as Fig. 1, however Fig. 3 has lower surface recesses, and in ¶ 0011, “a plurality of the semiconductor dies shown in FIG. 3 in accordance with additional embodiments of the present technology.”
So it would have been obvious to one of ordinary skill in the art that the “integrated circuit” 104 described for Fig. 1 in ¶ 0018, would also share that 104 in Fig. 3 is an “an integrated circuit structure” (from preamble).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “an integrated circuit structure” (from preamble), as disclosed by Fig. 1 of Zhou in the system of Figs. 3 and 8 of Zhou, for the purpose of utilizing a configuration of circuitry integrated in large scale on a diminutively sized semiconductor die, which allows for high device density per unit area, and thus increasing functionality. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 14, the prior art of Zhou discloses the integrated circuit die of claim 13, wherein the first width is a greater distance than the first depth (In Figs. 1, 3 and 8, Zhou discloses, “In some embodiments, the width W can be greater than the length L of the recesses 120, 122”, ¶ 0039).
Regarding claim 21, the prior art of Zhou discloses the integrated circuit die of claim 13, wherein the first planar bonding surface (Zhou Fig. 8 annotated ‘first bonding surface’, lower surface of 110) spans a plurality of metal bond pads (plural “conductive contacts 113”, ¶ 0019 shown and labeled in Fig. 3, and shown in Fig. 8) and a bonding interface layer (Zhou discloses in Fig. 8, wherein the annotated ‘first bonding surface’ is directly bonded to the ‘second bonding surface’, which includes both insulation material surface and conductive feature surfaces bonded to insulation and conductive surfaces, “passivation materials 111, 115 surround and electrically insulate the conductive contacts 113, 117”, ¶ 0019. So ‘second bonding surface’ of 100a would bond to the ‘first bonding surface’ of 100b, the “bonding interface layer” meaning the interface where the insulators bond to the insulators, and the conductors bond to the conductors).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou (US 2024/0047424) in view of Chen et al. (US 9,299,736).
Regarding claim 11, the prior art of Zhou discloses the integrated circuit structure of claim 10, however, Zhou does not specify,
“wherein the first bonding surface is fusion bonded with the second bonding surface.”
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Chen discloses in Fig. 8, “The annealing may be performed for a period of time between about 1 hour and 2 hours. When temperature rises, the OH bond in surface dielectric layers 126 and 226 break to form strong Si—O—Si bonds, and hence wafers 100 and 200 are bonded to each other through fusion bonds (and through Van Der Waals force). In addition, during the annealing, the metal (such as copper) in metal pads 124 and 224 diffuse to each other, so that metal-to-metal bonds are also formed. Hence, the resulting bonds between wafers 100 and 200 are hybrid bonds.”, col. 6, lines 2-11.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the first bonding surface is fusion bonded with the second bonding surface”, as disclosed by Chen in the system of Zhou, for the purpose of utilizing a configuration of bonding that ensures and very solid mechanical and electrical connection that is less prone to breakage. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claims 8, 9, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 8, the prior art of Zhou (US 2024/0047424) does not disclose the particular aspect of where the “wherein the first roof of the first edge recess is underneath the BEOL build-up structure”.
Claim 9 is objected to due to the dependence upon claim 8.
Regarding claim 19, the prior art of Zhou (US 2024/0047424) does not disclose the particular aspect of where the “wherein the first roof of the first edge recess is underneath the BEOL build-up structure”.
Claim 20 is objected to due to the dependence upon claim 19.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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