DETAILED ACTION
This correspondence is in response to the communications received June 26, 2026. Claims 1-13 and 20 are pending. Claims 14-19 have been withdrawn from consideration, see details below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant has made no claim to the benefit of an earlier filing date.
Election/Restrictions
Claims 14-19 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 26, 2026.
Relevant Prior Art
Yang (US 2014/0183724) Fig. 8, shown below.
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Wang (US 2005/0040520) Fig. 1B, shown below.
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Hembree et al. (US 6,242,931) Fig. 6A, shown below.
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Paglia et al. (US 2012/0018900) Fig. 11, shown below.
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Low et al. (US 6,329,278) Fig. 3, shown below.
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 5, an apparatus, comprising:
first electrical components (20), a respective first electrical component having first connection areas (24);
second electrical components (40), a respective second electrical component having second connection areas (44);
support assemblies (30), a respective support assembly (32) mounted to the respective first electrical component (top surface of 20) to limit a lateral range of movement of the respective second electrical component relative to the respective first electrical component (32’ limits lateral movement of electrodes of 40 with respect to facing electrodes of 20); and
masses of connection material (Fig. 3, elements 48 which become 49 by the step of Fig. 5) formed on at least one of the first connection areas or the second connection areas to at least partially connect corresponding ones of the first connection areas and the second connection areas (48/49 connect plural 24 to plural 44).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 9, 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Massingill et al. (US 5,413,964) in view of Ferguson et al. (US 10,260,961).
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Regarding claim 1, the prior art of Massingill discloses in Figs. 1-5, an apparatus (see title, “Photo-definable Template For Semiconductor Chip Alignment”), comprising:
first electrical components (“substrate 15”, col. 2, line 51), a respective first electrical component having first connection areas (“pads 16”, col. 2, line 52);
second electrical components (“chip 10”, col. 2, line 65), a respective second electrical component having second connection areas (“pads 11”, col. 2, line 65);
support assemblies (“alignment template 20”, col. 2, line 63), a respective support assembly mounted to the respective first electrical component to limit a lateral range of movement of the respective second electrical component relative to the respective first electrical component (20 is initially mounted to 15 prior to the bonding of chip 10, and 20 is used to guide 10 to be aligned such that 11 are in alignment with 16, “an alignment template 20 is formed on the top face of the substrate 15, shaped to receive the chip 10 and hold it in place while the pads 11 are bonded to the pads 16.”, col. 2, lines 63-66).
Massingill does not disclose, “masses of connection material formed on at least one of the first connection areas or the second connection areas to at least partially connect corresponding ones of the first connection areas and the second connection areas.”
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Ferguson discloses in Fig. 9, masses of connection material (“solder 104-1”, col. 7, line 10) formed on at least one of the first connection areas (equivalent element being “conductive contacts 110-1”, col. 7, line 8) or the second connection areas (equivalent element being “conductive contacts 102-1”, col. 7, line 7) to at least partially connect corresponding ones of the first connection areas and the second connection areas (104-1 connects 110-1 to 100-1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “masses of connection material formed on at least one of the first connection areas or the second connection areas to at least partially connect corresponding ones of the first connection areas and the second connection areas.”, as disclosed by Ferguson in the system of Massengill, for the purpose of allowing for a lower temperature electrical bond connection between the two electronic components. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Massengill et al. disclose the apparatus of claim 1, and Massengill discloses, wherein the respective support structure (20) is mounted to the respective first electrical component in an at least partially surrounding relation to the respective second electrical component (20 mounted to 15 before placement of 10 as can be seen in the progression of steps in Figs. 1 to 5).
Regarding claim 3, the prior art of Massengill et al. disclose the apparatus of claim 1, and Massengill discloses, wherein the first connection areas (16) of the respective first electrical component (15) are arranged in a first connection array (see array of 16 in Figs. 3-5).
Regarding claim 5, the prior art of Massengill et al. disclose the apparatus of claim 3, and Massengill discloses, wherein the respective support structure is mounted to the respective first electrical component in an at least partially surrounding relation to the first connection areas arranged in the first connection array (20 surrounds 10, and 20 is initially mounted on 15).
Regarding claim 9, the prior art of Massengill et al. disclose the apparatus of claim 1, wherein the support structures are formed of a photodefinable polyimide (discussed by Massengill in col. 3, lines 7-28).
Regarding claim 10, the prior art of Massengill et al. disclose the apparatus of claim 1, wherein an offset between sidewalls of the respective second electrical component and sidewalls of the respective support structure limits the lateral range of movement of the respective second electrical component (Massengill discloses the space between inner sidewall of 20 and outer side of 10 is discussed in col. 3, lines 29-40 with values for the spacing).
Regarding claim 20, the prior art of Massingill discloses in Figs. 1-5, an apparatus (see title, “Photo-definable Template For Semiconductor Chip Alignment”), comprising:
a first electrical component (“substrate 15”, col. 2, line 51) having first connection areas (“pads 16”, col. 2, line 52) arranged thereon in a first connection array (array of 16 shown);
a second electrical component (“chip 10”, col. 2, line 65) having second connection areas (“pads 11”, col. 2, line 65) arranged thereon in a second connection array (array of 11 shown),
the second electrical component (10) positioned on the first electrical component (15) such that the second connection areas are substantially aligned with corresponding ones of the first connection areas (plural 11 shown in positions corresponding to plural 16);
a support assembly (“alignment template 20”, col. 2, line 63) mounted to the first electrical component (20 mounted initially on 15, before 10 is mounted on 15) in an at least partially surrounding relation to the first connection areas in the first connection array (20 surrounds plural 11 on 15 before mounting 10, as can be seen in Figs. 3 and 4), the support assembly limiting a lateral range of movement of the second electrical component positioned on the first electrical component (20 is initially mounted to 15 prior to the bonding of chip 10, and 20 is used to guide 10 to be aligned such that 11 are in alignment with 16, “an alignment template 20 is formed on the top face of the substrate 15, shaped to receive the chip 10 and hold it in place while the pads 11 are bonded to the pads 16.”, col. 2, lines 63-66).
Massingill does not disclose, “connections between corresponding ones of the first connection areas and the second connection areas formed from masses of connection material on one or both of the first connection areas or the second connection areas.”
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Ferguson discloses in Fig. 9, connections between corresponding ones of the first connection areas (11) and the second connection areas (16) formed from masses of connection material (“solder 104-1”, col. 7, line 10) on one or both of the first connection areas or the second connection areas (ultimately on both 11 and 16 during bonding).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “connections between corresponding ones of the first connection areas and the second connection areas formed from masses of connection material on one or both of the first connection areas or the second connection areas”, as disclosed by Ferguson in the system of Massengill, for the purpose of allowing for a lower temperature electrical bond connection between the two electronic components. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 4 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Massingill et al. (US 5,413,964) in view of Ferguson et al. (US 10,260,961) in view of Olson et al. (US 2022/0238445).
Regarding claim 4, the prior art of Massengill et al. disclose the apparatus of claim 3, however Massengill does not disclose, “wherein the first connection array is at least partially defined by a first connection area pitch between adjacent ones of the first connection areas of from about 10 microns to about 40 microns.”
Olson discloses a chip on substrate solder ball connection arrangement where there pitches are as small as 10 micrometers at the bridge chip areas, and are mainly in the 20 micrometer pitch distances for the remainder of the package, see ¶ 0026.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the first connection array is at least partially defined by a first connection area pitch between adjacent ones of the first connection areas of from about 10 microns to about 40 microns”, as disclosed by Olson in the system of Massengill, for the purpose of allowing for increased electrical connection density to improve device functionality. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 6, the prior art of Massengill et al. disclose the apparatus of claim 4, and Massengill discloses, wherein the second connection areas of the respective second electrical component are arranged in a second connection array (array of 11 on surface of 10 as shown in Figs. 1, 2 and 5 of Massengill).
Regarding claim 7, the prior art of Massengill et al. disclose the apparatus of claim 6, however Massengill does not disclose, “wherein the second connection array is at least partially defined by a second connection area pitch between adjacent ones of the second connection areas of from about 10 microns to about 40 microns.”
Olson discloses a chip on substrate solder ball connection arrangement where there pitches are as small as 10 micrometers at the bridge chip areas, and are mainly in the 20 micrometer pitch distances for the remainder of the package, see ¶ 0026.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the second connection array is at least partially defined by a second connection area pitch between adjacent ones of the second connection areas of from about 10 microns to about 40 microns”, as disclosed by Olson in the system of Massengill, for the purpose of allowing for increased electrical connection density to improve device functionality. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 8, the prior art of Massengill et al. disclose the apparatus of claim 7, and Massengill discloses, wherein the second connection area pitch is substantially equal to the first connection area pitch (as can be seen in Figs. 1-5, the pitches between plural 11 and plural 16 are equal distances).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Massengill et al. (US 5,413,964) in view of Ferguson et al. (US 10,260,961) in view of Yamakawa (US 10,412,828) in view of Kasuya et al. (US 2010/0006995).
Regarding claim 12, the prior art of Massengill et al. disclose the apparatus of claim 1, however Massengill does not disclose, “wherein the first electrical components comprise an analog chip, an analog chiplet, an analog die or an analog wafer.”
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Yamakawa discloses 10 which has 11 core, where, “For example, a silicon substrate or a ceramic substrate may be used as the substrate body 11.” Where it is known in the art that a “silicon substrate” is a “semiconductor chip (silicon substrate)”, ¶ 0100 from Kasuya. The definition of analog is, “device in which information is represented by continuously variable physical quantities” (from Merriam-Webster.com), with example, “Copper telephone lines carry data in analog form”. Thus the “the wiring substrate 10 includes a substrate body 11” col. 3, lines 1-2 of Yamakawa, satisfies the analog requirement.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the first electrical components comprise an analog chip, an analog chiplet, an analog die or an analog wafer”, as disclosed by Yamakawa/Kasuya in the system of Massengill, for the purpose of utilizing a high density wiring configuration. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 13, the prior art of Massengill et al. disclose the apparatus of claim 12, however Massengill does not disclose, “wherein the second electrical components comprise a digital chip, a digital chiplet, a digital die or a digital wafer.”
Yamakawa discloses, “The semiconductor element 41 may be, for example, a logic chip such as a central processing unit (CPU) chip or a graphics processing unit (GPU) chip. The semiconductor element 41 may be, for example, a memory chip such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, or a flash memory chip.”, col. 4, lines 9-15. Memory chips rely on binary data which is digital information, thus satisfying the limitation.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the second electrical components comprise a digital chip, a digital chiplet, a digital die or a digital wafer”, as disclosed by Yamakawa in the system of Massengill, for the purpose of utilizing a chip capable of providing memory functionality. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
“11. (Original) The apparatus of claim 8, wherein the offset is from about 1 micron to about 3 microns.” Massengill only shows 0.5-1 MILS spacing, which is over 12 micrometers at the smallest.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
Prosecution Insights