DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 10468258).
Regarding claim 1, Lin discloses that a method of fabricating a semiconductor device, the method comprising:
forming on a substrate 46 a device isolation layer 70 defining an active pattern (Fig. 5A-7B);
forming a high-k dielectric layer 82 (col. 4, Lines 50-67+) on an upper portion of the active pattern 46, the upper portion protruding beyond the device isolation layer 44 (Fig. 1);
forming on the high-k dielectric layer 82 an impurity-doped layer containing an impurity; and performing an annealing process on the impurity-doped layer 88 to implant the impurity 87 into the high-k dielectric layer 82 (Fig. 5A-7B, col. 5, lines 15-43).
Reclaim 2, Lin discloses that a capping layer 86 between the high- k dielectric layer 82 and the impurity-doped layer 88, wherein during the annealing process, the impurity diffuses into the capping layer and the high-k dielectric layer (Fig. 5A-7B).
Reclaim 3, Lin discloses that selectively removing the impurity-doped layer; and forming a gate electrode on the capping layer (Fig. 8A-9A).
Reclaim 4, Lin discloses that an impurity concentration of the high-k dielectric layer is less than an impurity concentration of the capping layer (co. 6, lines 13-41).
Reclaim 5, Lin discloses that selectively removing the impurity-doped layer; selectively removing the capping layer; and forming a gate electrode on the high-k dielectric layer (Fig. 8A-9A).
Reclaim 6, Lin discloses that the impurity is selected from the group consisting of nitrogen (N), fluorine (F), phosphorous (P), boron (B), and a combination thereof (Fig. 8A-9A, note: fluorine).
Reclaim 7, Lin discloses that forming the high-k dielectric layer comprises: forming a first part on a sidewall of the upper portion of the active pattern; and forming a second part on a top surface of the upper portion of the active pattern (Fig. 8A-9A).
Reclaim 8, Lin discloses that forming a work function metal pattern on the high-k dielectric layer; and forming an electrode pattern on the work function metal pattern, wherein the work function metal pattern and the high-k dielectric layer contain the same impurity, and wherein an impurity concentration of the first part of the high-k dielectric layer is less than an impurity concentration of the work function metal pattern (Fig. 5A-9A).
Reclaim 9, Lin discloses that an impurity concentration of the first part is substantially a same as an impurity concentration of the second part (Fig. 5A-7A).
Reclaim 10, Lin discloses that, before forming the high-k dielectric layer, further comprising: forming a sacrificial pattern on the upper portion of the active pattern;
forming a pair of source/drain patterns on opposite sides of the sacrificial pattern, respectively; and selectively removing the sacrificial pattern to form an empty space exposing the upper portion of the active pattern (Fig. 5A-7A).
Regarding claim 11, Lin discloses that a method of manufacturing a semiconductor device comprising:
forming a first dielectric layer 82 ;
forming a silicon layer 88 (note: “The dummy layer 88 may include or be a silicon layer, for example a polysilicon layer or an amorphous silicon layer”) doped with impurities 87 over the first dielectric layer 82; and
annealing the silicon layer to cause some of the impurities to migrate from the silicon layer into the first dielectric layer and become implanted in the first dielectric layer (Fig. 5A-7A, col. 5, lines 15-43).
Reclaim 12, Lin discloses that the silicon layer is a polysilicon layer (“The dummy layer 88 may include or be a silicon layer, for example a polysilicon layer or an amorphous silicon layer”).
Reclaim 13, Lin discloses that forming a second dielectric layer between the first dielectric layer and the silicon layer, wherein the some impurities migrate through the second dielectric layer (Fig. 5A-6A, note: “ The gate dielectric layer 82 can be or include silicon oxide, silicon nitride, a high-k dielectric material, multilayers - -“).
Reclaim 14, Lin discloses that other impurities doped within the silicon layer migrate into, and become implanted within, the second dielectric layer by the annealing (note: “the dummy layer 88 may contain fluorine, deuterium, or both”).
Reclaim 15, Lin discloses that the annealing implants more impurities within the second dielectric layer than in the first dielectric layer (Fig. 5A-7A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 10468258) in view of Wang et al. (US 20200043927).
Reclaim 16, Lin fails to teach that forming a first electrode and a second electrode; forming a third electrode such that a portion of the third electrode is disposed directly between the first electrode and the second electrode; and forming a channel region disposed directly between the first electrode and the second electrode, wherein the first dielectric layer is formed to be disposed directly between the third electrode and each of the first electrode, second electrode and channel region.
However, Wang suggests that forming a first electrode 154 and a second electrode 154 (outer side) ; forming a third electrode 154 such that a portion of the third electrode is disposed directly between the first electrode 154 and the second electrode 154; and forming a channel region disposed directly between the first electrode and the second electrode, wherein the first dielectric layer is formed to be disposed directly between the third electrode and each of the first electrode, second electrode and channel region (21B).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Lin with forming a first electrode and a second electrode; forming a third electrode such that a portion of the third electrode is disposed directly between the first electrode and the second electrode; and forming a channel region disposed directly between the first electrode and the second electrode, wherein the first dielectric layer is formed to be disposed directly between the third electrode and each of the first electrode, second electrode and channel region as taught by Wang in order to improve complexity of device and yield rate and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Regarding claim 17, Lin & Wang disclose that a method of fabricating a semiconductor device, the method comprising:
forming a first semiconductor pattern 46 and a second semiconductor pattern 46 that are vertically stacked on a substrate 42, the first and second semiconductor patterns being vertically spaced apart from each other (Wang, Fig. 21A-B);
forming a high-k dielectric layer in a space between the first and second semiconductor patterns; forming an impurity-doped layer on the high-k dielectric layer 82, the impurity-doped layer 88 filing the space and containing an impurity 87 (Lin, Fig. 5A-7A); and performing an annealing process on the impurity-doped layer to implant the impurity into the high-k dielectric layer (Lin, Fig. 5A-7B, col. 5, lines 15-43).
Reclaim 18, Lin & Wang disclose that forming a first semiconductor layer, a sacrificial layer and a second semiconductor layer that arc sequentially stacked on the substrate; forming a pair of source/drain patterns, such that the first and second semiconductor patterns are formed from the first and second semiconductor layers and formed between the pair of source/drain patterns; and selectively removing the sacrificial layer to form the space between the first and second semiconductor patterns (Lin’s Fig. 5A-7B in view of Wang’s Fig. 21A-B).
Reclaim 19, Lin & Wang disclose that a capping layer 86 between the high-k dielectric layer 82 and the impurity-doped layer 88, wherein during the annealing process, the impurity diffuses into the capping layer and the high-k dielectric layer (Lin’s Fig. 5A-7B in view of Wang’s Fig. 21A-B).
Reclaim 20, Lin & Wang disclose that selectively removing the impurity-doped layer; and forming a gate electrode on the capping layer and filing the space (Fig. 7A-B. Lin).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 of U.S. Patent No. 11948994 in view of Lin et al. (US 10468258) and further in view of Wang et al. (US 20200043927).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11217677 in view of Lin et al. (US 10468258) and further in view of Wang et al. (US 20200043927).
Conclusion
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/SU C KIM/ Primary Examiner, Art Unit 2899