DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 7/2/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US 11948994 and US 11217677 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 9, 17, & 19-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng et al. (US 20200135475).
Regarding claim 1, Cheng discloses that a method of fabricating a semiconductor device, the method comprising:
forming on a substrate 206 a device isolation layer 210 defining an active pattern (Fig.2, para. 0020);
forming a high-k dielectric layer 504 on an upper portion of the active pattern 214, the upper portion protruding beyond the device isolation layer 210, wherein forming the high-k dielectric layer comprises:
forming a first part on a sidewall of the upper portion of the active pattern (Fig. 2); and
forming a second part on a top surface of the upper portion of the active pattern (Fig. 2);
forming on the high-k dielectric layer 504 an impurity-doped layer containing an impurity 602 (Fig. 7);
performing an annealing process on the impurity-doped layer to diffuse the impurity into the high-k dielectric layer (Fig. 7, para. 0034-0037, impurity-doped layer 602 and it becomes a source of nitrogen and diffused into the high-k dielectric material);
forming a work function metal pattern 602 (Fig. 7); and
forming an electrode pattern 906, 1002, 1202, 1204, 1206, 1208 , 1302 on the work function metal pattern, wherein the work function metal pattern and the high-k dielectric layer contain the impurity (Fig. 15).
Reclaim 2, Cheng discloses that a capping layer 603 between the high-k dielectric layer and the impurity-doped layer, wherein during the annealing process, the impurity diffuses into the capping layer and the high-k dielectric layer (Fig. 7).
Reclaim 3, Cheng discloses selectively removing the impurity-doped layer; and forming a gate electrode comprising the work function metal pattern and the electrode pattern on the capping layer (Fig. 15).
Reclaim 6, Cheng discloses that the impurity is selected from the group consisting of nitrogen (N), fluorine (F), phosphorous (P), boron (B), and a combination thereof (para. 0034, nitrogen).
Reclaim 9, Cheng discloses that an impurity concentration of the impurity in the first part is substantially a same as an impurity concentration of the impurity in the second part (Fig. 2 & 7).
Regarding claim 17, Cheng discloses that a method of fabricating a semiconductor device, the method comprising:
forming a first semiconductor pattern and a second semiconductor pattern that are vertically stacked on a substrate, the first and second semiconductor patterns being vertically spaced apart from each other (Fig. 2);
forming a high-k dielectric layer 504 (para. 0030) in a space vertically between the first and second semiconductor patterns (Fig. 2 & 6-7);
forming an impurity-doped layer 602 on the high-k dielectric layer 504 , the impurity-doped layer filing the space and containing an impurity; and
performing an annealing process on the impurity-doped layer to diffuse the impurity into the high-k dielectric layer (Fig. 7).
Reclaim 19, Cheng discloses that forming a capping layer 602 between the high-k dielectric layer 504 and the impurity-doped layer 603, wherein during the annealing process, the impurity diffuses into the capping layer and the high-k dielectric layer (Fig. 7).
Reclaim 20, Cheng discloses that selectively removing the impurity-doped layer; and forming a gate electrode on the capping layer and filing the space (Fig. 15).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 & 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200135475).
Reclaim 4, Cheng fails to specify that that an impurity concentration of the impurity in the high-k dielectric layer is less than an impurity concentration of the impurity in the capping layer.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain impurity concentration of the impurity in the high-k dielectric layer is less than an impurity concentration of the impurity in the capping layer, because it would have been to obtain a certain impurity concentration of the impurity in the high-k dielectric layer is less than an impurity concentration of the impurity in the capping layer to achieve suitable dielectric property of high-k dielectric.
Reclaim 8, Cheng fails to specify that an impurity concentration of the impurity in the first part of the high-k dielectric layer is less than an impurity concentration of the impurity in the work function metal pattern.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain an impurity concentration of the impurity in the first part of the high-k dielectric layer is less than an impurity concentration of the impurity, because it would have been to obtain a certain an impurity concentration of the impurity in the first part of the high-k dielectric layer is less than an impurity concentration of the impurity to achieve suitable dielectric property of high-k dielectric.
Claim(s) 10 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200135475) and further in view of Pan et al. (US 20180197970).
Reclaim 10, Cheng fails to teach that before forming the high-k dielectric layer, further comprising: forming a sacrificial pattern on the upper portion of the active pattern; forming a pair of source/drain patterns on opposite sides of the sacrificial pattern, respectively; and selectively removing the sacrificial pattern to form an empty space exposing the upper portion of the active pattern.
However, Pan suggests that before forming the high-k dielectric layer, further comprising:
forming a sacrificial pattern 34 on the upper portion of the active pattern 24 (Fig. 13B);
forming a pair of source/drain patterns 42 on opposite sides of the sacrificial pattern 34, respectively (Fig. 15B); and
selectively removing the sacrificial pattern 34 to form an empty space exposing the upper portion of the active pattern (Fig. 7).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Chen with before forming the high-k dielectric layer, further comprising: forming a sacrificial pattern on the upper portion of the active pattern; forming a pair of source/drain patterns on opposite sides of the sacrificial pattern, respectively; and selectively removing the sacrificial pattern to form an empty space exposing the upper portion of the active pattern as taught by Pan in order to enhance variation of process and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 18, Cheng & Pan disclose that forming a first semiconductor layer 30 , a sacrificial layer 24 and a second semiconductor layer 30 (polysilicon) that are sequentially stacked on the substrate 20 (Fig. 6B);
forming a pair of source/drain patterns 42, such that the first and second semiconductor patterns are formed from the first and second semiconductor layers 30 and formed between the pair of source/drain patterns (Pan, Fig. 6B); and
selectively removing the sacrificial layer 34 to form the space between the first and second semiconductor patterns 30, wherein the first semiconductor pattern and the second semiconductor pattern are configured as channels to connect the pair of source/drain patterns to one another (Fig. 7).
Allowable Subject Matter
Claims 11-12 & 15-16 are allowed over the prior art.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
After further search and consideration, it is determined that the prior art neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination.
The prior art does not teach or render not obvious “- - forming a silicon layer doped with impurities over the first dielectric layer;
forming a second dielectric layer between the first dielectric layer and the silicon layer;
annealing the silicon layer to cause the impurities to migrate from the silicon layer into the first dielectric layer and the second dielectric layer and become implanted in the first dielectric layer and the second dielectric layer - -” with combination of other claim limitations in claim 11 .
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SU C KIM/ Primary Examiner, Art Unit 2899
Prosecution Insights