Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/23/2025 have been fully considered but they are not persuasive. The applicant’s arguments hinge on the assertion that their invention “may vary the error correction capability in consideration of a case in which an increase in memory capacity is required or a case in which high-performance error correction capability is required” (see page 15 of the remarks). This is exactly what is Yu is already doing. ¶252 of Yu states “A third level ECC can be implemented by either RAIDS-like parity for all stripping data or by generating parity data for a stripe of block that needs extra protection.” (emphasis added). As such, it can be seen that Yu may add extra ECC capability for blocks that need extra protection, at the cost of extra storage, and not use it when it isn’t required, which allows for an increase in usable memory capacity (i.e. vary the error correction capability).
The applicant has failed to show how the claimed invention would NOT be obvious in view of the prior art. The KSRs allow for one of ordinary skill in the art to re-arrange parts of the prior art as long as the outcomes would be predictable, and the applicant has provided zero evidence to the contrary that their claimed invention produces any results that would be unexpected and could be relied upon to support an argument of non-obviousness. Not surprisingly, as this would be quite challenging as one of ordinary skill in the art would have a considerable knowledge of digital logic, logic gates, computer architecture, micro-controllers and integrated circuits of which the performance and connections of such are well understood and predictable (i.e. they all come with data sheets or their properties are well-known), and part layout/designs can easily be tested via software simulations.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (see pages 14-15 of the remarks where the applicant relies on ¶107 and figures 8A and 8B) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7, 8, and 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2015/0106556).
In regards to claim 1,
A memory system comprising: (fig. 1. SSD 102)
a plurality of memory modules; (fig. 1, flash mem 30, ¶78 each channel is attached to a number of flash chips (plurality of memory modules)
a [plurality] module controllers configured to respectively control the plurality of memory modules; (fig. 1, smart-storage switch controller)
a [plurality] of interface circuits configured to interface the plurality of memory modules with the plurality of module controllers, (fig. 1 multi-channel flash I/F, ¶78 allows the controller to write data into the flash chips of flash mem 30)
wherein, according to a setting signal, at least one target interface circuit is configured to transfer user data and an error correction code for the target memory module between a target module controller among the plurality of module controllers and a target memory module among the plurality of memory modules, or transfer extended error correction codes for other memory modules different from the target memory module between other module controllers different from the target module controller and the target memory module. (¶97-99, fig. 5 teaches different types of mappings that can be used to determine the physical address from the logical address provided by the host. The controller can use the mapping table to determine (or change) the channel that data is mapped to, and the physical channel part of the address/command (i.e. a set of bits that are set to identify/signal) are used to identify which memory module to access. ¶270 teaches that ECC can be stored with the data in spare portions of a page (i.e. ECC and data can be transferred to a single target memory module). ¶272 and ¶308 teaches that when extra protection is required, parity data can be generated (i.e. extended ECC) and can be sent to a different memory module that stores just the parity data (extended ECC).
Yu may not explicitly teach there are a plurality of memory controllers and/or a plurality of interface circuits. However, Yu does teach in ¶304 that multiple levels of controllers can be used, which could be beneficial because it would be less than complex. In ¶310 that bus architectures with nested or segmented buses could be used internally or externally, and more complex switch fabrics can be substituted for the internal or external bus. In ¶313 the system can be comprised of a multi-chip package, and in ¶314 that the flash channels can be organized in chains, branches, or arrays to connect to the smart storage switch (i.e. channel interface and controller).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to take these teachings/suggestions and modified the system to use multiple controllers and multiple interface modules for the single ones shown in fig. 1 and been able to interconnect these components through a switching fabric, such that they could perform the functions as claimed, and that one of ordinary skill in the art could replace the single controllers and interface modules with a plurality of them and the results would have been predictable. The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143 (B)). Furthermore, the courts have held that merely duplicating parts “has no patentable significance unless a new and unexpected result is produced”, and that rearranging of parts is “held to be an obvious matter of design choice“ (see MPEP 2144.04 VI (B) and (C)).
In regards to claim 2, Yu further teaches and/or makes obvious
wherein the target interface circuit is configured to transfer, between the target module controller and the target memory module, the user data and the error correction code for the target memory module, in response to the setting signal having a first logic level, and wherein the target interface circuit is configured to transfer, between the other module controllers and the target memory module, the extended error correction codes for the other memory modules different from the target memory module, in response to the setting signal having a second logic level. (¶60 teaches that ECC may be generated and stored with write data. ¶270-272 teaches the use of additional ECC techniques, such as generating additional ECC bits for pages that are later copied to the flash memory, and also using RAID-like parity and generating parity data for a stripe (¶97-99 teaches that one channel can be used for parity of the other channels).
In regards to claim 3, Yu further teaches and/or makes obvious
wherein each of the other module controllers is configured to generate user data and an error correction code for a corresponding memory module, generate the extended error correction code by increasing a size of the error correction code according to the setting signal, and output the extended error correction code to the target interface circuit. (¶60 teaches that ECC may be generated and stored with write data. ¶270-272 teaches the use of additional ECC techniques, such as generating additional ECC bits for pages that are later copied to the flash memory, and also using RAID-like parity and generating parity data for a stripe (¶97-99 teaches that one channel can be used for parity of the other channels).
In regards to claim 4, Yu further teaches and/or makes obvious
wherein each of the plurality of memory modules includes 2n memory packages, wherein n is a positive integer, and wherein, according to the setting signal, the target interface circuit is configured to transfer an extended error correction code for a first memory module among the other memory modules, to n memory packages of the target memory module, and transfer an extended error correction code for a second memory module among the other memory modules, to remaining n memory packages of the target memory module. (¶78 teaches each chip had D dies (i.e. 2N memory packages). ¶270 teaches that the amount of extended ECC bits is configurable and the extended ECC is stored in DRAM until written to the flash (i.e. written to a memory module). ¶62 teaches that data can be packed together and cached in the DRAM until it reaches the size of the page. Therefore, it could be set that the size of the extended ECC is equal to the width of N memory packages, allowing two sets of extended ECC (for different modules) to be cached in the DRAM and written together to a target module, where the first set of extended ECC is stored in N memory packages and second set of extended ECC is stored in the other N memory packages of a memory module.
In regards to claim 7, Yu further teaches and/or makes obvious
wherein each of the plurality of memory modules includes m memory packages, and wherein k memory packages are disposed to store the user data, and remaining (m-k) memory packages are disposed to store the error correction code, wherein m is a positive integer of 2 or more and k is a positive integer less than m. (¶78 teaches each chip had D dies, ¶319 teaches the size of sectors, pages, blocks can vary, ¶308 teaches parity/ECC can be written to separate area, ¶311 teaches parity and ECC can be implemented in a variety of ways, and ¶239 teaches that the more bits that are used for ECC, the more robust.) Therefore, one of ordinary skill in the art would have been able to choose a level of ECC such that the data and ECC were split between the available memory packages of a memory module.)
In regards to claim 8, Yu further teaches and/or makes obvious
wherein each of the plurality of memory modules includes m memory packages, wherein m is a positive integer of 2 or more, and the m memory packages are disposed to store the user data. (¶78 teaches each chip had D dies and ¶308 teaches parity/ECC can be written to a separate area (i.e. to another memory module/package besides the ones storing user data)
In regards to claims 13 and 18, Yu teaches
first to third memory modules; (fig. 1, flash mem 30, ¶78 each channel is attached to a number of flash chips (i.e. A first to third memory modules)
first [to third] module controller[s] configured to generate user data and an error correction code for the first to third memory modules, respectively; (¶60 teaches ECC manager 28 of the storage switch controller 40 (see fig. 1) generates ECC to attach to write data to be written to the flash memory 30 (which contains the first to third memory modules)
first [to third] interface circuit[s] configured to transmit and receive the user data and the error correction code to and from the first to third memory modules, respectively, through independent channels (fig. 1, multi-channel flash I/F 14, ¶79 teaches each channel can be access at the same time (i.e. independent), ¶60 data can be read/written across the channels to the flash memory (via the multi-channel I/F), which can contain the write (user) data and ECC)
wherein the first [and second] module controller[s] are configured to respectively increase a size of the error correction code according to a setting signal to generate first and second extended error correction codes (¶60 teaches that ECC may be generated and stored with write data. ¶270-272 teaches the use of additional ECC techniques, such as generating additional ECC bits for pages that are later copied to the flash memory (i.e. first and second extended ECC), and also using RAID-like parity and generating parity data for a stripe (¶97-99 teaches that one channel can be used for parity of the other channels).
wherein the [third] interface circuit is configured to transmit/receive the first and second extended error correction codes to/from the third memory module according to the setting signal. (¶270-272 teaches the use of additional ECC techniques, such as generating additional ECC bits for pages that are later copied to the flash memory (i.e. transmitted/received through the multi-channel interface)
Yu may not explicitly teach there are a plurality of memory controllers and/or a plurality of interface circuits. However, Yu does teach in ¶304 that multiple levels of controllers can be used, which could be beneficial because it would be less than complex. In ¶310 that bus architectures with nested or segmented buses could be used internally or externally, and more complex switch fabrics can be substituted for the internal or external bus. In ¶313 the system can be comprised of a multi-chip package, and in ¶314 that the flash channels can be organized in chains, branches, or arrays to connect to the smart storage switch (i.e. channel interface and controller)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to take these teachings/suggestions and modified the system to use multiple controllers and multiple interface modules for the single ones shown in fig. 1 and been able to interconnect these components through a switching fabric, such that they could perform the functions as claimed, and that one of ordinary skill in the art could replace the single controllers and interface modules with a plurality of them and the results would have been predictable. The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (see MPEP 2143 (B)). Furthermore, the courts have held that merely duplicating parts “has no patentable significance unless a new and unexpected result is produced”, and that rearranging of parts is “held to be an obvious matter of design choice“ (see MPEP 2144.04 VI (B) and (C)).
In regards to claims 14 and 19, Yu further teaches and/or makes obvious
wherein each of the first and second extended error correction codes includes a size corresponding to half of a number of bits of the user data and the error correction code. (¶270 teaches that the amount of extended ECC bits is configurable. Therefore, it could be set that the size of the extended ECC can be set to any desired amount.
In regards to claim 15 and 20, Yu further teaches and/or makes obvious
wherein the first to third interface circuits are configured to respectively transmit and receive x-bit user data and a y-bit error correction code to and from the first to third memory modules, in response to the setting signal having a first logic level, and wherein the first and second interface circuits are configured to respectively transmit and receive x-bit user data and a y-bit error correction code to and from the first and second memory modules, and the third interface circuit is configured to transmit and receive the first and second extended error correction codes each having a (x + y)/2-bit size, to and from the third memory module, in response to the setting signal having a second logic level. ¶270 teaches that the amount of ECC and extended ECC bits is configurable and the extended ECC is stored in DRAM until written to the flash (i.e. written to a memory module). ¶60 teaches that ECC may be generated and stored with write data, as such it can be chosen to be x-bits of user data and y-bits of ECC. ¶62 teaches that data can be packed together and cached in the DRAM until it reaches the size of the page. Therefore, it could be set that the size of the extended ECC is equal to (x + y)/2-bit, allowing two sets of extended ECC (for different modules) to be cached in the DRAM and written together to any memory module and to be received later if needed (see fig. 22B step 736, SW ECC is the extended ECC).
In regards to claim 16, Yu further teaches and/or makes obvious
wherein each of the first to third memory modules includes 2n memory packages, wherein n is a positive integer, and wherein, according to the setting signal, the third interface circuit is configured to transmit and receive the first extended error correction code to and from n memory packages of the third memory module, and transmit and receive the second extended error correction code to and from remaining n memory packages of the third memory module. (¶270 teaches that the amount of extended ECC bits is configurable and the extended ECC is stored in DRAM until written to the flash (i.e. written to a memory module). ¶62 teaches that data can be packed together and cached in the DRAM until it reaches the size of the page. Therefore, it could be set that the size of the extended ECC is equal to the width of N memory packages, allowing two sets of extended ECC (for different modules) to be cached in the DRAM and written together to a target module, where the first set of extended ECC is stored in N memory packages and second set of extended ECC is stored in the other N memory packages of a memory module.
In regards to claim 17, Yu further teaches and/or makes obvious
wherein the setting signal is generated based on a request from a host. (fig. 1, data is requested to be read/written by host 100 via host I/F 16. ¶65 teaches commands from the host can be used to monitor and control error correction. Furthermore, host commands for read/write contain a logical address that is used to be translated to a physical address (see ¶97-99) that can be associated with a page status that indicates the level of ECC to use)
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2015/0106556) in view of Ma (US 2008/0320214).
In regards to claim 5, Yu teaches
wherein each of the plurality of memory modules includes 2n memory packages, wherein n is a positive integer, (¶78 teaches each chip had D dies (i.e. 2N memory packages)
Yu may not explicitly teach the inner details of the interface signal lines to include strobe and upper/lower data lines as claimed:
wherein the target interface circuit is coupled to n memory packages of the target memory module through first data lines transmitting upper data and a first strobe line transmitting an upper strobe signal, and coupled to remaining n memory packages of the target memory module through second data lines transmitting lower data and a second strobe line transmitting a lower strobe signal.
However, Ma teaches in fig. 19A/B and ¶143 that there can be an upper data line (DQ[15:8] and lower data line DQ[7:0] that use data strobes DSQ1 and DSQ2.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date to be able to modify the system of Yu to use teachings of Ma in order to connect the interfaces to individual chips/dies, etc…. The rationale to support a conclusion that the claim would have been obvious is that since Yu doesn’t provide the specific lower level connections on how the data is written from an interface into a part of a memory, and therefore one of ordinary skill in the art could incorporate any lower level elements, such as those taught by Ma to accomplish the tasks of writing the data with predictable results.
In regards to claim 6, Yu teaches
wherein each interface circuit except for the target interface circuit, among the plurality of interface circuits, is coupled to 2n memory packages of a corresponding memory module (¶78 teaches each chip had D dies (i.e. 2N memory packages)
Ma teaches
through data lines transmitting upper and lower data and a strobe line transmitting a strobe signal. (fig. 19A/B and ¶143 that there can be an upper data line (DQ[15:8] and lower data line DQ[7:0] that use data strobes DSQ1 and DSQ2.)
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2015/0106556) in view of Applicant Admitted Prior Art (AAPA).
In regards to claims 9 and 10, Yu teaches
In Fig 1, a multi-channel flash interface circuit 14 and ¶305 teaches that serial busses can be used with any number/arrangements.
Yu doesn’t explicitly teach that the interface includes
Receivers/transmitters, selection circuits, serializers/deserializers to send/receive data (i.e. lower/upper parts) between the controller and memory modules.
The applicant has admitted that electronic parts (and accompanying digital logic layouts) to perform these functions are well known and ubiquitous to one of ordinary skill in the art prior to the effective filing date of the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to use such parts in the design of an interface circuit, such as claimed, in order to facilitate the reading and writing of data between a controller and memory module. The individual arrangement and connection of these parts is but a design choice. The motivation for incorporating these parts/connections is that the could be used to implement an I/O interface with predictable results.
In regards to claim 11, Yu teaches
a host interface circuit (fig. 1, host I/F 16)
however Yu doesn’t explicitly teach that it is
configured to communicate with a host using a high-speed interconnect interface for the memory system and an accelerator communication, compliant with a compute express link (CXL) interface.
The applicant has admitted that high speed interfaces such as CXL interfaces were known in the art prior to the effective filing date of the claimed invention, therefore it would have been obvious to one of ordinary skill in the art to have incorporated a host interface that is capable of communicating using a CXL interface. The motivation for such modification is that it allows the system to be used with host that are capable of using CXL.
In regards to claim 12, Yu teaches
That the system can be an SSD (see fig. 1, SSD 102)
However, Yu doesn’t explicitly teach the form factor in which the SSD takes (such as an Add-in Card, or EDSFF)
The applicant has admitted that both Add-in-Card and Enterprise and Data Center SSD Form Factor (EDSFF) where known in the art prior to the effective filing date of the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have incorporated the SSD into either of these form factors. The motivation for such modification is that it allows the SSD to be used with system that use/require these specific form factors.
EXAMINER’S NOTE
Examiner has cited particular paragraphs, figures, and/or columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The applicant is reminded of what constitutes a proper reply to this office action is detailed in 37 CFR 1.111, and that the examiner has the discretion to treat any response that fails to meet ALL the requirements of that section as NON-RESPONSIVE without any additional extensions of time (see MPEP 714.03).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON W BLUST/Primary Examiner, Art Unit 2132