DETAILED ACTION
This Action is responsive to the Amendment filed on 07/31/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5-6, 13, 15, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fulford (US 2023/0245929).
Regarding claim 1, Fulford (see, e.g., FIG. 6, FIG. 9) discloses a semiconductor device comprising:
first source/drain regions 511, 513 connected through a first channel structure 514 which is controlled by a first gate structure 112 (Para 0025, Para 0033, Para 0035, Para 0036); and
second source/drain regions 521, 523, respectively above the first source/drain regions 511, 513, connected through a second channel structure 524 which is controlled by a second gate structure 122 (Para 0027, Para 0037),
wherein:
the first gate structure 112 overlaps the first channel structure 514 in a first direction e.g., x-direction,
the second gate structure 122 overlaps the second channel structure 524 in the first direction e.g., x-direction,
a length d1 of the first gate structure 112 in a second direction e.g., y-direction is different from a length d2 of the second gate structure 122 in the second direction e.g., y-direction,
the first channel structure 514 and the second channel structure 524 comprise different materials (Para 0033, Para 0035, Para 0037), and
the first direction e.g., x-direction intersects the second direction e.g., y-direction.
Regarding claim 3, Fulford (see, e.g., FIG. 6, FIG. 9) teaches the semiconductor device of claim 1, wherein a length of the first channel structure 514 in the second direction e.g., y-direction is different from a length of the second channel structure 524 in the second direction e.g., y-direction in which the first source/drain regions 511, 513 are connected and the second source/drain regions 521, 523 are connected (Para 0035, Para 0037).
Regarding claim 5, Fulford (see, e.g., FIG. 6, FIG. 9) teaches the semiconductor device of claim 1, wherein a length of the first source/drain regions 511, 513 in the second direction e.g., y-direction is different from a length of the source/drain regions 521, 523 in the second direction e.g., y-direction.
Regarding claim 6, Fulford (see, e.g., FIG. 6, FIG. 9) teaches the semiconductor device of claim 5, wherein the length of the first source/drain regions 511, 513 in the second direction e.g., y-direction is smaller than the length of the second source/drain regions 521, 523 in the second direction e.g., y-direction.
Regarding claim 13, Fulford (see, e.g., FIG. 6, FIG. 9) discloses a semiconductor device comprising:
first source/drain regions 511, 513 connected through a first channel structure 514 which is controlled by a first gate structure 112 (Para 0025, Para 0033, Para 0035, Para 0036); and
second source/drain regions 521, 523, respectively above the first source/drain regions 511, 513, connected through a second channel structure 524 which is controlled by a second gate structure 122 (Para 0027, Para 0037),
wherein
the first gate structure 112 overlaps the first channel structure 514 in a first direction e.g., x-direction,
the second gate structure 122 overlaps the second channel structure 524 in the first direction e.g., x-direction,
a length d1 of the first gate structure 112 in a second direction e.g., y-direction is different from a length d2 of the second gate structure 122 in the second direction e.g., y-direction (Para 0025, Para 0027),
a length of the first channel structure 514 in the second direction e.g., y-direction is different from a length of the second channel structure 524 in the second direction e.g., y-direction in which the first source/drain regions 511, 513 are connected and the second source/drain regions 521, 523 are connected (Para 0033, Para 0035, Para 0037), and
the first direction e.g., x-direction intersects the second direction e.g., y-direction.
Regarding claim 15, Fulford (see, e.g., FIG. 6, FIG. 9) teaches the semiconductor device of claim 13, wherein a length of the first source/drain regions 511, 513 in the second direction e.g., y-direction is different from a length of the second source/drain regions 521, 523 in the second direction e.g., y-direction.
Regarding claim 21, Fulford (see, e.g., FIG. 6, FIG. 9) discloses a semiconductor device comprising:
first source/drain regions 511, 513 connected through a first channel structure 514 which is controlled by a first gate structure 112 (Para 0025, Par 0033, Para 0035, Para 0036); and
second source/drain regions 521, 523, respectively above the first source/drain regions 511, 513, connected through a second channel structure 524 which is controlled by a second gate structure 122 (Para 0027, Para 0037),
wherein
the first gate structure 112 overlaps the first channel structure 514 in a first direction e.g., x-direction,
the second gate structure 122 overlaps the second channel structure 524 in the first direction e.g., x-direction,
a length d1 of the first gate structure 112 in a second direction e.g., y-direction is different from a length d2 of the second gate structure 122 in the second direction e.g., y-direction in which the first source/drain regions 511, 513 are connected and the second source/drain regions 521, 523 are connected (Para 0033, Para 0035, Para 0037), and
the first direction e.g., x-direction intersects the second direction e.g., y-direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Fulford (US 2023/0245929), in view of Li (US 2024/0047455).
Regarding claim 2, although Fulford shows substantial features of the claimed invention, Fulford fails to expressly teach the semiconductor device of claim 1, wherein the first channel structure comprises silicon germanium (SiGe), and the second channel structure comprises silicon (Si).
Li (see, e.g., FIG. 1) teaches that the first channel structure 132 (of upper FET 104A) comprises silicon germanium (SiGe), and the second channel structure 132 (of lower FET 106A) comprises silicon (Si) for the purpose of utilizing p-type material and n-type material to form p-type devices and n-type devices (Para 0030, Para 0034).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the first channel structure and the material of the second channel structure of Fulford to the first channel structure comprising silicon germanium (SiGe) and the second channel structure comprising silicon (Si) for the purpose of utilizing p-type material and n-type material to form p-type devices and n-type devices (Para 0034).
Regarding claim 9, Fulford (see, e.g., FIG. 6, FIG. 9) teaches the semiconductor device of claim 1, wherein a length of the first channel structure 514 in the second direction e.g., y-direction is different from a length of the second channel structure 524 in the second direction e.g., y-direction in which the first source/drain regions 511, 513 are connected and the second source/drain regions 521, 523 are connected (Para 0033, Para 0035, Para 0037).
Although Fulford shows substantial features of the claimed invention, Fulford fails to expressly teach that the first channel structure comprises silicon germanium (SiGe), and the second channel structure comprises silicon (Si).
Li (see, e.g., FIG. 1) teaches that the first channel structure 132 (of upper FET 104A) comprises silicon germanium (SiGe), and the second channel structure 132 (of lower FET 106A) comprises silicon (Si) for the purpose of utilizing p-type material and n-type material to form p-type devices and n-type devices (Para 0030, Para 0034).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the first channel structure and the material of the second channel structure of Fulford to the first channel structure comprising silicon germanium (SiGe) and the second channel structure comprising silicon (Si) for the purpose of utilizing p-type material and n-type material to form p-type devices and n-type devices (Para 0034).
Allowable Subject Matter
Claims 4, 7-8, 10-12, 14, 17-18, 20, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1, 13, and 21 have been considered but are moot because of the new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Prosecution Insights