DETAILED ACTION
This action is responsive to the following communication: the response filed 6/18/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-20 pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9, 11, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0350441) in view of Mirichigni et al. (US 2019/0198099 ‒hereinafter Mirichigni).
Regarding claim 1, Kim discloses a method by a memory device, comprising:
applying (S811; fig. 8A) a voltage (i.e. a read voltage) to a plurality of memory cells (the read voltage applied in a read operation S811 may change a state of a plurality of memory cells; para 0021, 0160);
applying (S830; fig. 8A) a first voltage (an optimal read voltage applied in a second read operation S830; para 0164) based on a number of memory cells (the optimal read voltage is applied based on “comparing the range of the accumulated number of cells, which is obtained through the obtained information bits at step S814, with the information of the number of cells read” para 0164) in the plurality that switched (i.e. turned on) based on applying the voltage (“according to the read voltage” applied in the read operation S811; para 0164);
applying a second voltage (another optimal read voltage is applied in determining “NO” at S840; fig. 8A para 0167); and
determining (S840; fig. 8A) that one or more memory cells (i.e. any number of memory cells) in the plurality of memory cells store a first logic value (binary values corresponding to a range of accumulated number of cells; para 0163-0167) based on the one or more memory cells having switched (i.e. turned on) during one of the applying the voltage (i.e. the read voltage) and the applying the first voltage or based on the memory cell not having switched during the applying the second voltage (the binary values are determined based on applying the read voltage and the first voltage; fig. 8A).
Kim does not expressly disclose applying, for a duration, a voltage that changes over the duration, the voltage that changes over the duration.
Mirichigni discloses applying, for a duration (a Time duration; fig. 4A, 4B), a voltage (i.e. a read voltage) that changes over the duration (the read voltage 405 (405-a, 405-b) increases over the Time duration; fig. 4A, 4B), the voltage that changes over the duration (i.e. increase over the Time duration).
Changing biases during data accessing schemes are common and well known in the art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim is modifiable as taught by Mirichigni for the purpose of facilitating data accessing schemes by enhancing read techniques to compensate for variable electrical characteristics (para 0004 of Mirichigni), which is consistent with known practices in the prior art to avoid points of failure that could otherwise hinder a complex system.
Regarding claim 9, Kim discloses the method, further comprising: identifying a threshold voltage at which a threshold number of memory cells have switched (fig. 7A), wherein the threshold number of memory cells is associated with a codeword (i.e. accumulation index; para 0121-0123) or a page.
Regarding claim 11, Kim discloses the method, wherein applying the first voltage comprises: applying the first voltage based on the number of switched memory cells reaching a threshold number (fig. 7A).
Regarding claim 13, Kim discloses a memory device, comprising:
a plurality of memory cells (memory cell array 210; fig. 4A); and
circuitry (220; fig. 4A) coupled with the plurality of memory cells (106) and configured to cause the memory device (200; fig. 4A) to:
apply (S811; fig. 8A) a voltage (i.e. a read voltage) to the plurality of memory cells (read voltage applied in a read operation S811 may change a state of a plurality of memory cells; para 0021, 0160);
apply (S830; fig. 8A) a first voltage (an optimal read voltage applied in a second read operation S830; para 0164) based on a number of memory cells (the optimal read voltage is applied based on “comparing the range of the accumulated number of cells, which is obtained through the obtained information bits at step S814, with the information of the number of cells read” para 0164) in the plurality that switched (i.e. turned on) based on applying the voltage (“according to the read voltage” applied in the read operation S811; para 0164);
apply a second voltage (another optimal read voltage is applied in determining “NO” at S840; fig. 8A para 0167); and
determine (S840; fig. 8A) that one or more memory cells (i.e. any number of memory cells) in the plurality of memory cells store a first logic value (binary values corresponding to a range of accumulated number of cells; para 0163-0167) based on the one or more memory cells having switched (i.e. turned on) during one of the applying the voltage (i.e. the read voltage) and the applying the first voltage or based on the memory cell not having switched during the applying the second voltage (the binary values are determined based on applying the read voltage and the first voltage; fig. 8A).
Kim does not expressly disclose apply, for a duration, a voltage that changes over the duration, the voltage that changes over the duration.
Mirichigni discloses applying, for a duration (a Time duration; fig. 4A, 4B), a voltage (i.e. a read voltage) that changes over the duration (the read voltage 405 (405-a, 405-b) increases over the Time duration; fig. 4A, 4B), the voltage that changes over the duration (i.e. increase over the Time duration).
Changing biases during data accessing schemes are common and well known in the art. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim is modifiable as taught by Mirichigni for the purpose of facilitating data accessing schemes by enhancing read techniques to compensate for variable electrical characteristics (para 0004 of Mirichigni), which is consistent with known practices in the prior art to avoid points of failure that could otherwise hinder a complex system.
Claim(s) 2-4, 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0350441) in view of Mirichigni et al. (US 2019/0198099 ‒hereinafter Mirichigni), and further in view of Kim et al. (US 2010/0214819 ‒hereinafter Kim).
Regarding claim 2, Kim discloses the method, further comprising: latching a first set of data read from the plurality (i.e. via latches; para 0061, 0088).
Kim does not expressly disclose based on ending application of the first voltage.
Kim ‘819 discloses latching a first set of data read from the plurality (during LATCH period latching LCH is activated; fig. 16) based on ending application of the first voltage (ending application of read voltage 1.3 V when REN is deactivated; fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim is further modifiable as taught by Kim ‘819 for the purpose of controlling data accessing schemes such that a lifetime of memory cells are improved, which is common and well known in the art for increasing the integrity of data storage (para 0128 of Kim ‘819).
Regarding claim 3, Kim does not expressly disclose the method, wherein latching the first set of data and ending application of the first voltage occur at a same time.
Kim ‘819 discloses wherein latching the first set of data and ending application of the first voltage occur at a same time (i.e. a same time when REN is deactivated and latching LCH is activated; fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim is further modifiable as taught by Kim ‘819 for the purpose of controlling data accessing schemes such that a lifetime of memory cells are improved, which is common and well known in the art for increasing the integrity of data storage (para 0128 of Kim ‘819).
Regarding claim 4, Kim discloses the method, wherein the second voltage is applied after the first voltage (fig. 8A), the method further comprising: latching a second set of data read from the plurality (i.e. via latches; para 0061, 0088).
Kim does not expressly disclose based at least in part on ending application of the second voltage.
Kim ‘819 discloses latching a set of data read from the plurality (during LATCH period latching LCH is activated; fig. 16) based on ending application of a voltage (ending application of read voltage 1.3 V when REN is deactivated; fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim (i.e. during the second read operation) is further modifiable as taught by Kim ‘819, to end application of the voltage (i.e. the second voltage) during the second read operation of Kim, for the purpose of controlling data accessing schemes such that a lifetime of memory cells are improved, which is common and well known in the art for increasing the integrity of data storage (para 0128 of Kim ‘819).
Regarding claim 14, Kim discloses the memory device, wherein the circuitry is further configured to cause the memory device to: latch a first set of data read from the plurality (i.e. via latches; para 0061, 0088).
Kim does not expressly disclose based on ending application of the first voltage.
Kim ‘819 discloses latching a first set of data read from the plurality (during LATCH period latching LCH is activated; fig. 16) based on ending application of the first voltage (ending application of read voltage 1.3 V when REN is deactivated; fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim is further modifiable as taught by Kim ‘819 for the purpose of controlling data accessing schemes such that a lifetime of memory cells are improved, which is common and well known in the art for increasing the integrity of data storage (para 0128 of Kim ‘819).
Regarding claim 15, Kim does not expressly disclose the memory device, wherein latching the first set of data and ending application of the first voltage occur at a same time.
Kim ‘819 discloses wherein latching the first set of data and ending application of the first voltage occur at a same time (i.e. a same time when REN is deactivated and latching LCH is activated; fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim is further modifiable as taught by Kim ‘819 for the purpose of controlling data accessing schemes such that a lifetime of memory cells are improved, which is common and well known in the art for increasing the integrity of data storage (para 0128 of Kim ‘819).
Regarding claim 16, Kim discloses the memory device, wherein the second voltage is applied after the first voltage (fig. 8A), the circuitry is further configured to cause the memory device to: latching a second set of data read from the plurality (i.e. via latches; para 0061, 0088).
Kim does not expressly disclose based at least in part on ending application of the second voltage.
Kim ‘819 discloses latching a set of data read from the plurality (during LATCH period latching LCH is activated; fig. 16) based on ending application of a voltage (ending application of read voltage 1.3 V when REN is deactivated; fig. 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim (i.e. during the second read operation) is further modifiable as taught by Kim ‘819, to end application of the voltage (i.e. the second voltage) during the second read operation of Kim, for the purpose of controlling data accessing schemes such that a lifetime of memory cells are improved, which is common and well known in the art for increasing the integrity of data storage (para 0128 of Kim ‘819).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2018/0350441) in view of Mirichigni et al. (US 2019/0198099 ‒hereinafter Mirichigni), and further in view of Derhacobian (US 9,007,814).
Regarding claim 12, Kim does not expressly disclose the method, wherein the first voltage has a first polarity and the second voltage has a second polarity opposite to the first polarity.
Derhacobian discloses wherein the first voltage has a first polarity and the second voltage has a second polarity opposite to the first polarity (column/line(s): 28/58-63).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kim is further modifiable as taught by Derhacobian for the purpose of facilitating data accessing schemes during a read operation to mitigate read disturbances (column/line(s): 28/51-57 of Derhacobian), which is common and well known in the art for increasing the integrity of data storage.
Allowable Subject Matter
Claim(s) 5-8, 10, 17-20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
The allowable claims are supported in at least 3A-3B of the instant application.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN SMET whose telephone number is (571) 272-2267. The examiner can normally be reached M-F, 9 AM-5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/UYEN SMET/
Primary Examiner, Art Unit 2824______
Prosecution Insights