DETAILED ACTION
This correspondence is in response to the communications received April 24, 2026. Claims 1-10 are pending. Claims 1, 6, 9 and 10 have been amended.
Response to Arguments
Applicant’s argument regarding claim 1 and 10 rejections, where it is asserted that Ootorii previous interpretation of top electrode system 51, not disclosing the newly amended claim language of, “top electrode system disposed in the openings of the planarization layer”, is not found to be convincing. As the previous configuration of the claims were fully satisfied by that interpretation. However, now with the newly amended claim language, the interpretation of Ootorii has been shifted to include that the top electrode system includes both of 51 and 12, where 12 resides within the opening in the planarization layer 35, see the rejections below for full details. It is further noted, that Applicant’s own top electrode system 112 in Fig. 1, only partially resides within planarization layer 108.
Regarding claim 3, the office action has fully addressed the limitations of this claim as can be seen in the rejection below. No specific arguments have been provided to specifically address, beyond stating that the rejection is insufficient.
Regarding claim 4, the office action has fully addressed the limitations of this claim as can be seen in the rejection below. No specific arguments have been provided to specifically address, beyond stating that the rejection is insufficient.
Regarding claims 6-7, the office action has fully addressed the limitations of this claim as can be seen in the rejection below. No specific arguments have been provided to specifically address, beyond stating that the rejection is insufficient.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
A restriction requirement of a species requirement was initially contemplated, however the content either grouped electrodes, common top electrode and common bottom electrode are understood to be common variants of each other, see claims 3-5.
Claim Rejections - 35 USC § 112
Applicant’s amendment to claim 6 has overcome the 112 rejection which is hereby withdrawn.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 1, an integrated system comprising:
a micro-device structure comprising:
a micro-device array (array of microdevices 106) including one or more micro-devices (¶ 0005);
a bottom electrode system (104) for actuating the micro-device array;
a planarization layer (108) surrounding one or more the micro-devices (106), the planarization layer including openings to enable access to the one or more micro devices (access from above where 110 access 106); and
a backplane (114, ¶ 0046) including a top electrode system (“top electrodes 112”, ¶ 0046) disposed in the openings of the planarization layer (where openings 110 accommodate a trace and via shaped electrode, where the lower via portion resides in 108, while the top portion of 112 resides outside and on top of 108) for actuating each micro-device of the one or more micro devices, the top electrode system separated from the bottom electrode system by the planarization layer (see Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 8, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ootorii et al. (US 2012/0256814) in view of Yeo et al. (US 2017/0005158).
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Regarding claim 1, the prior art of Ootorii discloses in Fig. 1B, an integrated system (system with integrated components of at least light emitting diodes and thin film transistors discussed in ¶ 0003) comprising:
a micro-device structure (“pixel chip 1”, ¶ 0055) comprising:
a micro-device array including one or more micro devices (array of plural 11, including 11R, 11G, 11B, where “light emitting devices 11”, ¶ 0061 are “micro LED”, ¶ 0060);
a bottom electrode system (“solder layer 48, a wiring layer 47, a wiring layer 46, a via 45, a wiring layer 44, a via 43, a wiring layer 42, and a solder layer 41”, ¶ 0063, hereinafter referred to as ‘BES’) for actuating the micro-device array (BES connect the micro LED 11 to “driver IC 20”, ¶ 0064, where the actuation occurs by electrical signals from the driving chip 20 signals through BES to the plural 11);
a planarization layer (35, ¶ 0063, where 35 is clearly shown as a material which fills gaps between each light emitter and ultimately has a planar top surface) surrounding the one or more micro-devices (35 surrounding 11), the planarization layer including openings to enable access to the one or more micro devices (discontinuities over each 11, the “openings” interpreted as being the discontinuities where 12 reside); and
a backplane (The term “backplane” will be addressed in the combination rejection below. The element interpreted to be said backplane are the, “insulating layer 36 into which the wiring layer 51”, ¶ 0077, and the “first electrode 12”, ¶ 0062) including a top electrode system (the interpreted “top electrode system” includes features 51 and 12) disposed in the openings of the planarization layer (portions 12 are formed within the openings in 35 immediately above each 11) for actuating each micro-device of the one or more micro devices (51 provides driving signals to the 11 from the driver 20), the top electrode system separated from the bottom electrode system by the planarization layer (36/51/12 are separated from BES by way of at least 35).
The “top electrode system” of Ootorii is not explicitly labeled as a “backplane”.
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Yeo discloses in Fig. 2, wherein the pixel driving circuit region which is called a “TFT substrate” is also called a “backplane”, ¶ 0049.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of the understanding that the “top electrode system” is a “backplane”, as disclosed by Yeo in the system of Ootorii, for the purpose of providing for the required electrical connections to operate the light emitting array. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Ootorii et al. disclose the system according to claim 1, and Ootorii does not disclose wherein the backplane is composed of TFTs, however Yeo does disclose, wherein the backplane comprises a thin film transistor (TFT) structure (“a TFT substrate or a backplane”, ¶ 0049, where ‘TFT’ means “thin film transistor”).
Regarding claim 5, the prior art of Ootorii et al. disclose the system according to claim 1, and Ootorii discloses, wherein the top electrode system comprises a common top electrode (51, in Fig. 1B); and
wherein the bottom electrode system comprises a patterned electrode system including individual electrodes for each micro-device (BES are individual electrodes for each 11), and
wherein the common top electrode comprises a transparent material enabling light generated by the micro-devices to pass therethrough (¶ 0064, “wiring layer 51 may be made of a transparent conductive material (for example, ITO)”).
Regarding claim 8, the prior art of Ootorii et al. disclose the system according to claim 1, and Ootorii discloses in Fig. 1B, wherein the micro-device structure includes a substrate (layer 37, ¶ 0063) for supporting the micro-device array (supports the elements above).
Regarding claim 9, the prior art of Ootorii et al. disclose the system according to claim 8, wherein the micro-device structure includes a buffer layer (31, ¶ 0063) between the bottom electrode system (BES) and the substrate (37).
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Regarding claim 10, the prior art of Ootorii discloses in Fig. 1B (viewed “upside down”), a method of integrating a micro device structure (1, “pixel chip 1”, ¶ 0065) with a backplane electrical control system (20, “the driver IC 20”, ¶ 0065), comprising:
providing a micro-device structure (portion of 11, 35 and 12/51 of 1, “micro device” aspect will be addressed below) comprising:
a micro-device array including one or more micro devices (array of plural 11, including 11R, 11G, 11B, where “light emitting devices 11”, ¶ 0061 are “micro LED”, ¶ 0060, hereinafter referred to as ‘MDA’);
a bottom electrode system (“first electrode 12 … wiring layer 51”, ¶ 0066, hereinafter referred to as ‘BES’) for actuating the micro-device array (BES used to operate the array of 11 in MDA, carrying electrical signals from driver 20);
a planarization layer (35, ¶ 0063, where 35 is clearly shown as a material which fills gaps between each light emitter and ultimately has a planar top surface) surrounding the one or more micro-devices (35 surrounding plural 11), the planarization layer including openings to enable access to the one or more micro devices (The “openings” are interpreted to be the discontinuities in 35 over each 11, where 48 reside. These openings in 35 accommodate the portion 48 over 11); and
mounting a backplane (20, “driver IC 20”, ¶ 0064) on the micro-device structure (20 mounted on MDA),
the backplane including a top electrode system (The “top electrode system” is interpreted to be the combination of features of, “solder layer 48, a wiring layer 47, a wiring layer 46, a via 45, a wiring layer 44, a via 43, a wiring layer 42, and a solder layer 41”, ¶ 0063, hereinafter referred to as ‘TES’) disposed in the openings of the planarization layer (portion 48 of the TES is formed in the opening in 35 immediately above 12) for actuating each micro-device of the one or more micro devices (each 11 is supplied with its own electrical connection), the top electrode system separated from the bottom electrode system by the planarization layer (TES is separated from BES by 35).
The “top electrode system” of Ootorii is not explicitly labeled as a “backplane”.
Yeo discloses in Fig. 2, wherein the pixel driving circuit region which is called a “TFT substrate” is also called a “backplane”, ¶ 0049.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of the understanding that the “top electrode system” is a “backplane”, as disclosed by Yeo in the system of Ootorii, for the purpose of providing for the required electrical connections to operate the light emitting array. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ootorii et al. (US 2012/0256814) in view of Yeo et al. (US 2017/0005158) in view of Wu (US 2017/0220150).
Regarding claim 3, the prior art of Ootorii et al. disclose the system according to claim 1, however Ootorii discloses the opposite configuration, so Ootorii does not disclose,
“wherein the bottom electrode system comprises a common bottom electrode; and
wherein the top electrode system comprises a patterned electrode system including individual electrodes for each micro-device.”
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Wu discloses in Fig. 6,
wherein the bottom electrode system comprises a common bottom electrode (where “one anode 30 (common electrode)”, ¶ 0026); and
wherein the top electrode system comprises a patterned electrode system including individual electrodes (plural 50) for each micro-device (equivalent devices 4).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the bottom electrode system comprises a common bottom electrode; and
wherein the top electrode system comprises a patterned electrode system including individual electrodes for each micro-device.”, as disclosed by Wu in the system of Ootorii, for the purpose of providing for the required electrical connections to operate the light emitting array. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ootorii et al. (US 2012/0256814) in view of Yeo et al. (US 2017/0005158) in view of Lerman et al. (US 2011/0193114) in view of Yamazaki et al. (US 2012/0161167).
Regarding claim 4, the prior art of Ootorii et al. disclose the system according to claim 3, however Ootorii does show the top and bottom electrode configuration, but not the particular wiring arrangement of,
“wherein the top electrode system comprises a first and second groups of series electrodes connecting first and second groups of micro devices, respectively, in series; and
first and second column electrodes for connecting the first and second groups of series electrodes in parallel.”
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Lerman discloses in Figs. 20A to 20C,
wherein the top electrode system (198) comprises a first (upper group in Fig. 20C) and second groups (lower group in Fig. 20C) of series electrodes (198, 194) connecting first and second groups of micro devices (two groups of two), respectively, in series (series shown).
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Yamazaki discloses in Fig. 9B,
first (left most finger of 133a) and second column (middle most finger of 133b) electrodes for connecting the first (one of the intervening series connected group of three 1100) and second groups (other one of the intervening series connected group of three 1100) of series electrodes in parallel (parallel connection between the two identified first and second columns of series strings therebetween).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the top electrode system comprises a first and second groups of series electrodes connecting first and second groups of micro devices, respectively, in series; and
first and second column electrodes for connecting the first and second groups of series electrodes in parallel.”, as disclosed by Lerman/Yamazaki in the system of Ootorii, for the purpose of providing for the required electrical connections to operate the light emitting array. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Ootorii et al. (US 2012/0256814) in view of Yeo et al. (US 2017/0005158) in view of Bok et al. (US 2017/0269749).
Regarding claim 6, the prior art of Ootorii et al. disclose the system according to claim 5, however Ootorii does not disclose, “wherein a color conversion layer is disposed over the common top electrode for converting the light to a different color.”
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Bok discloses in Fig. 19, wherein a color conversion layer (1901, ¶ 0165) is disposed over the common top electrode (The “common top electrode” is interpreted to be the construction including 334, “second electrode 334 may be a common electrode.”, ¶ 0094 and 1902. The 1901 is formed “on top” of at least portion 334) for converting the light to a different color (“A color filter 1901 may be arranged over the LED 325. The color filter 1901 may transform light emitted from the LED 325 or increase color purity.”, ¶ 0165. The very definition of a “color filter” is that it is a layer whose only aim is that color is manipulated in some way, which satisfies “for converting light to a different color”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein a color conversion layer is disposed over the common top electrode for converting the light to a different color”, as disclosed by Bok in the system of Ootorii, for the purpose of tuning the outgoing light to a desired wavelength for the purpose of improving visual communication. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 7, the prior art of Ootorii et al. disclose the system according to claim 1, but does not disclose, “wherein the backplane comprises a touch sensing structure.”
Bok discloses in Fig. 12, wherein the backplane comprises a touch sensing structure (element 1128, 1129 are part of a touch sensing structure, ¶ 0132, where the backplane is every component under the pixel electrode 328, where 1128, 1129 are included in an interpretation in said backplane).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the backplane comprises a touch sensing structure”, as disclosed by Bok in the system of Ootorii, for the purpose of allowing the user to physically interact and input control information to operate the display device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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