DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 9-13 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koo et al. (US 20160211350) in view of Kakizaki et al. (US 6326279).
Regarding claim 1, Koo discloses that a method of manufacturing a semiconductor device, comprising:
forming a first insulator or a first conductor layer 125 on a first substrate 110;
forming a porous layer 120 on the first insulator or the first conductor layer 125;
forming a first film including a first device 130 & 140 (para. 0054), above the porous layer 120 (Fig. 4);
Koo fails to specify that a porous layer by anodization and forming a second film including a second device, on a second substrate; bonding the first substrate and the second substrate to sandwich the first insulator or the first conductor layer, the porous layer, the first film, and the second film; and separating the first substrate and the second substrate such that the first insulator or the first conductor layer and a first portion of the porous layer remain above the first substrate, and a second portion of the porous layer remains above the second substrate.
However, Kakizaki suggests that forming a second film 17 including a second device, on a second substrate 16 (Fig. 1F-H);
bonding the first substrate (Koo’s substrate in Fig. 4) and the second substrate 16 to sandwich the first insulator or the first conductor layer 125, the porous layer 120, the first film, 130 & 140 and the second film 17 (Kakizaki’s Fig. 1F) Fig. ; and
separating the first substrate and the second substrate such that the first insulator or the first conductor layer and a first portion of the porous layer remain above the first substrate, and a second portion of the porous layer remains above the second substrate (Fig. 1I) and a porous layer by anodization (col. 17, line 10).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Koo with forming a second film including a second device, on a second substrate; bonding the first substrate and the second substrate to sandwich the first insulator or the first conductor layer, the porous layer, the first film, and the second film; and separating the first substrate and the second substrate such that the first insulator or the first conductor layer and a first portion of the porous layer remain above the first substrate, and a second portion of the porous layer remains above the second substrate a porous layer by anodization as taught by Kakizaki in order to enhance adding insulating layer on the top of device layer and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
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Koo & Kakizaki fail to teach that a thick ness of the first insulator being 20 nm or less.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of the first insulator, because it would have been to obtain a certain thickness of the first insulator to achieve compact size of device.
Reclaim 2, Koo & Kakizaki disclose that removing the first portion from the first substrate, after separating the first substrate and the second substrate (Fig. 1F-1H).
Reclaim 3, Koo & Kakizaki disclose that the first portion is removed from the first substrate by CMP (Chemical Mechanical Polishing) or wet etching (Kakizaki, Fig. 1H) .
Reclaim 4, Koo & Kakizaki disclose that an etching selectivity between the first insulator or the first conductor layer and the first substrate is higher than an etching selectivity between the porous layer and the first substrate (Kakizaki, Fig. 1H) .
Reclaim 5, Koo & Kakizaki disclose that the porous layer is a semiconductor layer (Kakizaki, Fig. 1H, note: a porous silicon) .
Reclaim 6, Koo & Kakizaki disclose that the semiconductor layer includes p-type impurity atoms or n-type impurity atoms (Kakizaki, Fig. 1H, Col. 6, lines 34-67, note: “The porous layer may be formed by, e.g., anodization or ion implantation.”) .
Reclaim 7, Koo & Kakizaki disclose that a concentration of the p-type impurity atoms or the n-type impurity atoms in the semiconductor layer is 2.5x10²⁰ atoms/cm³ or more (Col. 6, lines 34-67, note: - -“form by diffusion, e.g., a 10.sup.18 /cm.sup.3 -boron-doped layer in a thickness as large as 10 .mu.m, the boron density reaches 10.sup.19 /cm.sup.3 to 10.sup.20 /cm.sup.3 in the vicinity of the surface in the initial stage of diffusion, so that defects tend to be brought into it”).
Reclaim 9, Koo & Kakizaki disclose that a porosity of the porous layer is 40% or more (Col. 6, lines 34-67, note: “The porous layer suited for the dividing may have a porosity usually ranging from 10% to 80%, and preferably from 20% to 60%.”)
Reclaim 10, Koo & Kakizaki disclose that a thickness of the porous layer is 100 to 20000 nm (Col. 6, lines 34-67, “The low-porosity layer may preferably have a thickness of from 0.1 .mu.m to 100 .mu.m & The high-porosity layer may preferably have a thickness of 5 .mu.m at maximum.”).
Reclaim 11, Koo & Kakizaki fail to specify that a resistivity of the porous layer is equal to or less than a two-thousandth of a resistivity of the first substrate.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain resistivity of a substrate because it would have been to obtain a certain resistivity of a substrate to achieve suitable protection to device layers.
Reclaim 12, Koo & Kakizaki fail to teach that a resistivity of the first substrate is 20 to 30 Ω.cm.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain resistivity of a substrate because it would have been to obtain a certain resistivity of a substrate to achieve suitable protection to device layers.
Reclaim 13, Koo & Kakizaki disclose that the first insulator includes silicon (Koo, para. 0064, SiNx).
Reclaim 18, Koo & Kakizaki disclose that the first device includes a memory cell array, and the second device includes a circuit that controls the memory cell array (Fig. 4).
Allowable Subject Matter
Claims 19-25 are allowed over the prior art.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
After further search and consideration, it is determined that the prior art neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination.
The prior art does not teach or render not obvious “- - forming a porous layer on the first conductor layer;
forming a first film including a first device, above the porous layer;
forming a second film including a second device, on a second substrate;
bonding the first substrate and [[a]] the second substrate to sandwich the first insulator or the first conductor layer and the porous layer; and
separating the first substrate and the second substrate such that the first insulator or the first conductor layer and a first portion of the porous layer remain above the first substrate, and a second portion of the porous layer remains above the second substrate, wherein the first device includes a memory cell array, and the second device includes a circuit that controls the memory cell array.” with combination of other claim limitations in claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed on 8/7/2026 have been fully considered but they are not persuasive.
With respect to rejected claims under 35 U.S.C. 103, applicant argues that “fails to teach a porous layer - - by anodization”
In response to applicant's contention, it is respectfully submitted that Kakizaki discloses all the claimed limitation including “a porous layer - - by anodization” below.
Kakizaki appears to show, see , col. 17, line 10 and a porous layer can be made by anodization.
Also, Koo & Kakizaki fail to specify that a thickness of the first insulator being 20 nm or less.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of the first insulator, because it would have been to obtain a certain thickness of the first insulator to achieve compact size of device.
Therefore, the rejection of claims 1-3, 5-6 and 7 under 35 U.S.C. 103 is deemed proper and the prima facie case of obviousness has been met and the rejection under 35 U.S.C. § 103 is deemed proper.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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/SU C KIM/Primary Examiner, Art Unit 2899
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