DETAILED ACTION
This Office Action is in response to the Election filed on July 7, 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species A, claims 1-7 in the reply filed on July 7, 2027 is acknowledged.
Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (WO 2023/227321 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In re claim 1, Xie et al. shows (figs. 47 and 48) a semiconductor device, comprising: a plurality of gates (264) separated by an interlayer dielectric (ILD) (260); a backside contact (282), wherein: the backside contact is extended below the plurality of gates and a dielectric layer; and the backside contact is extended from a first gate to a second gate of the plurality of gates (the backside contact flares out laterally); and a placeholder (250), wherein: the placeholder is extended below the plurality of gates, and between the second gate (fig. 48; left gates 264) and a third gate (fig. 48; middle gate 264) of the plurality of gates; and the backside contact and the placeholder are not directly electrically connected (not electrically connected to each other).
In re claim 2, Xie et al. shows (figs. 47 and 48) a backside interlayer dielectric (BILD) (fig. 28; 234) below the plurality of gates; and a shallow trench isolation (STI) (280)within the BILD and over the backside contact.
In re claim 3, Xie et al. shows (figs. 47 and 48) the STI isolates the backside contact from direct contact with a gate and the ILD, and wherein the BILD isolates the placeholder and the backside contact from directly connecting to each other.
In re claim 4, Xie et al. shows (figs. 47 and 48) the STI is made of at least one of silicon dioxide and silicon nitride; and the dielectric layer is made of silicon dioxide [0085].
In re claim 5, Xie et al. shows (figs. 47 and 48) a source/drain region (254) above the placeholder.
In re claim 6, Xie et al. shows (figs. 47 and 48) a source/drain contact (266) above the source/drain region electrically connecting the source/drain region to a back end of line (BEOL) (268) on a frontside of the semiconductor device.
In re claim 7, Xie et al. shows (figs. 47 and 48) a plurality of nanosheets (212) extended horizontally along each of the plurality of gates.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hong et al. (US Pub. 2025/0151362 A1).
In re claim 1, Hong et al.shows (fig. 2) a semiconductor device, comprising: a plurality of gates (115, 21A, 21B, 21C) separated by an interlayer dielectric (ILD) (162); a backside contact (250), wherein: the backside contact is extended below the plurality of gates and a dielectric layer; and the backside contact is extended from a first gate to a second gate of the plurality of gates (the backside contact flares out laterally); and a placeholder (104), wherein: the placeholder is extended below the plurality of gates, and between the second gate (21A) and a third gate (21B) of the plurality of gates; and the backside contact and the placeholder are not directly electrically connected (not electrically connected to each other).
In re claim 2, Hong et al. (fig. 2) a backside interlayer dielectric (BILD) (103) below the plurality of gates; and a shallow trench isolation (STI) (105) within the BILD and over the backside contact.
In re claim 3, Hong et al. (fig. 2) the STI isolates the backside contact from direct contact with a gate and the BILD, and wherein the BILD isolates the placeholder and the backside contact from directly connecting to each other.
In re claim 4, Hong et al. (fig. 2) the STI is made of at least one of silicon dioxide and silicon nitride; and the dielectric layer is made of silicon dioxide [0049].
In re claim 5, Hong et al. (fig. 2) a source/drain region (130R) above the placeholder.
In re claim 6, Hong et al. (fig. 2) a source/drain contact (170) above the source/drain region electrically connecting the source/drain region to a back end of line (BEOL) (190) on a frontside of the semiconductor device.
In re claim 7, Hong et al. (fig. 2) a plurality of nanosheets (112) extended horizontally along each of the plurality of gates.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Qin (US Pub. 2025/0220987 A1), Vega (US Pub. 2025/0204048 A1), Mukesh (US Pub. 2025/0203989 A1), Jung (US Pub. 2025/0203930 A1), Park (US Pub. 2025/0194215 A1), Lee (US Pub. 2024/0274676 A1), Choi (KR-20250124702-A), Kim (KR-20250109005-A), and Minchul (EP-4478404-A1) also disclose various elements of the claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2817
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