DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9-16 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 21, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (2023/0402385, hereafter Lin) in view of Chen et al. (2015/0235940, hereafter Chen), Hsu et al. (2017/0092771, hereafter Hsu), and Okina (2021/0202382, hereafter Okina).
Regarding claim 1, Lin discloses a semiconductor device, comprising: a substrate (102); a first metal layer (108) on said substrate; a first dielectric layer (106b) on said first metal layer (108); a dual damascene metal structure (V_x) extending through said first metal layer (108) and said first dielectric layer (106b); a layer (107) between said dual damascene metal structure and said first metal layer; and an other (112) layer on said layer (107) and between said dual damascene metal structure and said layer (107); wherein a top surface of said layer is lower than a top surface of said first dielectric layer (Fig. 3).
Lin fails to disclose a dual damascene structure partly in said substrate.
However, Chen teaches a dual damascene structure (204, Fig. 2, par. 0033) partly in said substrate (102, Fig. 2, par. 0033).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin with Chen by providing a dual damascene structure partly in the substrate in order to establish a low-resistance, mechanically secure contact interface.
Lin and Chen fail to disclose a specifically oxide-semiconductor layer and metal-oxide layer (said other layer) comprising at least two metal elements.
However, Hsu teaches an oxide-semiconductor layer (308, Fig. 6, par. 0040) and metal-oxide layer (said other layer) (306, Fig. 6, par. 0039) comprising at least two metal elements.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin and Chen with Hsu by providing an oxide-semiconductor layer and a metal-oxide layer in order to provide a thinner interface that reduces copper resistance and suppresses electromigration, thus improving functionality.
Lin, Chen, and Hsu fail to disclose the other layer directly contacts said top surface of said first dielectric layer and said top surface of said oxide-semiconductor layer, and a top surface of said metal oxide layer is lower than a top surface of said dual damascene metal structure.
However, Okina teaches the other layer directly (84L) contacts said top surface of said first dielectric layer (874) and said top surface of said layer (82P), and a top surface of said other layer is lower than a top surface of said dual damascene metal structure (86L) (Fig. 10).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin, Chen, and Hsu with Okina by providing an inner layer contacting the dielectric and outer liner but being lower than the metal structure in order to encapsulate the metal at the interface to eliminate diffusion leakage and prevent electromigration.
Regarding claim 2, Lin fails to disclose a semiconductor device wherein said metal oxide layer completely covers said oxide-semiconductor layer and partly on said top surface of said first dielectric layer.
However, Chen teaches a semiconductor device wherein said other layer (124) completely covers said layer (122) and partly on said top surface of said first dielectric layer (115) (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin with Chen by providing the metal-oxide layer over the oxide-semiconductor layer and partly over the dielectric layer in order to create a continuous seal that prevents copper diffusion and improves interfacial adhesion.
Lin and Chen fail to disclose an oxide-semiconductor layer and a metal oxide layer.
However, Hsu teaches an oxide-semiconductor layer (308, Fig. 6, par. 0040) and metal-oxide layer (said other layer) (306, Fig. 6, par. 0039).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin and Chen with Hsu by providing an oxide-semiconductor layer and a metal-oxide layer in order to provide a thinner interface that reduces copper resistance and suppresses electromigration, thus improving functionality.
Regarding claim 3, Lin discloses a semiconductor device wherein said dual damascene metal structure comprises a lower part (V_x) between said layer (107) and an upper part (M_[x+1]) covering a top surface of said other layer (112) (Fig. 5C).
Lin and Chen fail to disclose a specifically oxide-semiconductor layer and metal oxide layer.
However, Hsu teaches an oxide-semiconductor layer (308, Fig. 6, par. 0040) and metal-oxide layer (said other layer) (306, Fig. 6, par. 0039).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin and Chen with Hsu by providing an oxide-semiconductor layer and a metal-oxide layer in order to provide a thinner interface that reduces copper resistance and suppresses electromigration, thus improving functionality.
Regarding claim 4, Lin discloses semiconductor device wherein said upper part (M_[x+1]) of said dual damascene metal structure has a first maximum width (W1), said other layer (112) on said top surface of said first dielectric layer (106b) has a second maximum width (W2), and said first maximum width is larger than said second maximum width (Fig. 5B-5C).
Lin and Chen fail to disclose a specifically metal oxide layer.
However, Hsu teaches a metal-oxide layer (said other layer) (306, Fig. 6, par. 0039).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin and Chen with Hsu by providing an oxide-semiconductor layer and a metal-oxide layer in order to provide a thinner interface that reduces copper resistance and suppresses electromigration, thus improving functionality.
Regarding claim 5, Lin discloses a semiconductor device wherein said layer (107) is provided with ladder feature (Fig. 3).
Lin and Chen fail to disclose an oxide-semiconductor layer.
However, Hsu teaches an oxide-semiconductor layer (308, Fig. 6, par. 0040).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin and Chen with Hsu by providing an oxide-semiconductor layer and a metal-oxide layer in order to provide a thinner interface that reduces copper resistance and suppresses electromigration, thus improving functionality.
Regarding claim 7, Lin discloses a semiconductor device wherein said dual damascene metal structure comprises a barrier layer (107) and a metal layer (V_x) on said barrier layer (Fig. 3).
Regarding claim 19, Lin, Hsu, and Chen fail to disclose a semiconductor device wherein the dual damascene metal structure comprises a lower part between the oxide-semiconductor layer and an upper part covering the top surface of the metal oxide layer.
However, Okina teaches a semiconductor device wherein the dual damascene metal structure (86L) comprises a lower part (86L lower) between the oxide-semiconductor layer (82P) and an upper part (86L upper) covering the top surface of the metal oxide layer (84L) (Fig. 10).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin, Hsu, and Chen with Okina by providing an upper part of the metal structure that covers the metal oxide in order to completely seal the barrier, ensuring maximum structural adhesion, preventing stress and eliminating diffusion.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chen, Hsu, and Okina as applied to claim 1 above, and further in view of Li et al. (2022/0319989, hereafter Li).
Regarding claim 6, Lin and Chen, discussed above, fail to disclose a semiconductor device further comprising an insulating layer on a top surface of said oxide-semiconductor layer and between said first dielectric layer and said metal oxide layer.
However, Li teaches a semiconductor device further comprising an insulating layer (122, par. 0014) on a top surface of said oxide-semiconductor layer (120, par. 0014) and between said first dielectric layer (118, par. 0014) and said metal layer (126, par. 0015) (Fig. 1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin and Chen with Li by implementing an insulating layer on the top surface of an oxide-semiconductor layer in order to provide a capping barrier that suppresses electromigration and prevents copper diffusion.
Li does not explicitly teach an insulator that is specifically a metal-oxide layer.
However, Li teaches a metal-oxide interfacial layer (134, Fig. 1, par. 0012). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Li by implementing a metal-oxide insulator in order to minimize capacitive delay and providing a barrier against copper migration.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chen, Hus, and Okina as applied to claim 1 above, and further in view of Weng et al. (2007/0052107, hereafter Weng).
Regarding claim 8, Lin, Chen, Hsu, and Okina, discussed above, fail to disclose a semiconductor device further comprising a second dielectric layer between said substrate and said first metal layer.
However, Weng teaches a semiconductor device further comprising a second dielectric layer (204, par. 0051) between said substrate (200, par. 0051) and said first metal layer (206, par. 0051) (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin, Chen, Hsu, and Okina with Weng by implementing a second dielectric layer between the substrate and metal layer in order to provide electrical isolation and structural control for the integrated profile of the device.
Claims 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Hsu and Chen.
Regarding claim 17, Lin discloses a semiconductor device, comprising: a substrate (102, Fig. 1); a first metal layer (108, Fig. 3) on the substrate; a first dielectric layer (106b, Fig. 3) on the first metal layer; a hole (V_x, Fig. 3) passing through the first metal layer and the first dielectric layer and exposing the substrate; and a dual damascene metal structure (M_(x+1), Fig. 3) in the hole and covering a sidewall; wherein the top surface of the layer (107) is lower than a top surface of the first dielectric layer (106b) and the top surface of the other layer (112) (Fig. 3).
Lin fails to disclose an oxide-semiconductor layer and a metal oxide layer.
However, Hsu teaches an oxide-semiconductor layer (308, Fig. 6, par. 0040) and metal-oxide layer (said other layer) (306, Fig. 6, par. 0039).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin with Hsu by providing an oxide-semiconductor layer and a metal-oxide layer in order to provide a thinner interface that reduces copper resistance and suppresses electromigration, thus improving functionality.
Lin and Hsu fail to disclose a layer in the hole covering a sidewall of the hole and the substrate, an other layer on the layer covering a sidewall and a top surface of the layer and extending up above the first dielectric layer; and the metal structure covers a top surface of the other layer.
However, Chen teaches a layer (122) in the hole covering a sidewall of the hole and the substrate (204), an other layer on the layer (124) covering a sidewall and a top surface of the layer and extending up above the first dielectric layer (115); and the metal structure (208) covers a top surface of the other layer (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin and Hsu with Chen by providing an other layer covering the top surface of the layer and dielectric with the metal structure covering the other layer in order to encapsulate the metal at the interface to eliminate diffusion leakage and prevent electromigration.
Regarding claim 18, Lin and Hsu fail to disclose a semiconductor device wherein the metal oxide layer completely covers the oxide-semiconductor layer and partly on the top surface of the first dielectric layer.
However, Chen teaches a semiconductor device wherein the metal oxide layer (124) completely covers the oxide-semiconductor layer (122) and partly on the top surface of the first dielectric layer (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin and Hsu with Chen by providing a metal layer covering an oxide-semiconductor layer and partly on the dielectric layer in order to encapsulate the metal at the interface to eliminate diffusion leakage and prevent electromigration.
Regarding claim 20, Lin discloses a semiconductor device the oxide-semiconductor layer (107)is provided with ladder feature (Fig. 3).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.B./ Examiner, Art Unit 2817
/ALI NARAGHI/ Primary Examiner, Art Unit 2817
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