Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Non_Final office is a response to the papers filed on 02/26/2024.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Giuliano et al. (“Design and Sign-off Methodologies for Wafer-To-Wafer Bonded 3D-ICs at Advanced Nodes”, Cadence Design Systems, San Jose, USA, 2021)..
Regarding claim 1, Giuliano discloses:
A structure comprising:
a first chip having first chip metal levels including a first chip last metal level, wherein the first chip last metal level has a first chip last metal level pitch (see Fig. 9, top die, see page 22, col 2, map the package terminals to the last metal layer of the BS-PDN on the bottom die…., see page 17, col 2, Pitches for die to-die interconnect are typically around 40µm,……);
a second chip having second chip metal levels including a second chip last metal level, wherein the second chip last metal level has a second chip last metal level pitch (see Fig. 9, bottom die, see page 22, col 2, map the package terminals to the last metal layer of the BS-PDN on the bottom die…., see page 17, col 2, Pitches for die to-die interconnect are typically around 40µm,……); and
bonding elements connecting the first chip last metal level and the second chip last metal level (see Fig. 2-3, wafer-to-wafer bonding, see Fig. 9, bonding pads, see page , 18, see page 22, face-to-face (F2F) mapping file is required between the two dies so that the bonding pads can be used as sources for the top die once the current has effectively crossed the bottom one….), wherein the bonding elements have a bonding pitch that is at least as large as the first chip last metal level pitch and at least as large as the second chip last metal level pitch (see Fig. 2-3, see Fig, 9, see page 17, col. 2 and page 18, [wherein the size of bonding based pitches base on the interconnect technology and the requirement. Therefore, the ponding pitch can be as large as the first chip last metal level pitch and as large as the second chip top metal level pitch]).
Regarding claims 13 and 17, Giuliano discloses:
A method comprising:
receiving, by a processor from a user through a graphic user interface, two selections from a menu (see page 10-20 the physical design methodology for 3D-IC is using a graphic user interface which includes menu for selection),
wherein the selections are based on a preliminary design of a three-dimensional integrated circuit (3DIC) that includes partial designs for a first chip and a second chip of the 3DIC (see page 10-20 the physical design methodology for 3D-IC, see A. netlist partitioning for 3D page 19-20),
wherein the partial designs of the first chip and the second chip are devoid of any metal levels, wherein the menu includes selectable options, each option specifying a metal stack configuration including a last metal level pitch and further specifying a bonding pitch at least as large as the last metal level pitch (see page 19-20 the physical design methodology for 3D-IC is using a graphic user interface which includes menu for selection, see Fig. 2-3, see Fig, 9, see page 17, col. 2 and page 18, [wherein the size of bonding based pitches base on the interconnect technology and the requirement. Therefore, the ponding pitch can be as large as the first chip last metal level pitch and as large as the second chip top metal level pitch], see page 22),
wherein the two selections include:
an initial selection from the menu and a subsequent selection from only the selectable options on the menu that have the same bonding pitch as the initial selection, and wherein the two selections indicate (see page 19-20 the physical design methodology for 3D-IC is using a graphic user interface which includes menu for selection, see Fig. 2-3, see Fig, 9, see page 17, col. 2 and page 18, [wherein the size of bonding based pitches base on the interconnect technology and the requirement. Therefore, the ponding pitch can be as large as the first chip last metal level pitch and as large as the second chip top metal level pitch], see page 22):
a first chip metal stack configuration for first chip metal levels of the first chip, wherein the first chip metal stack configuration defines a first chip last metal level pitch (see Fig. 9, top die, see page 22, col 2, map the package terminals to the last metal layer of the BS-PDN on the bottom die…., see page 17, col 2, Pitches for die to-die interconnect are typically around 40µm,……);
a second chip metal stack configuration for second chip metal levels of the second chip, wherein the second chip metal stack configuration defines a second chip last metal level pitch (see Fig. 9, bottom die, see page 22, col 2, map the package terminals to the last metal layer of the BS-PDN on the bottom die…., see page 17, col 2, Pitches for die to-die interconnect are typically around 40µm,……); and
the bonding pitch for bonding elements connecting the first chip and the second chip in the 3DIC (see Fig. 2-3, wafer-to-wafer bonding, see Fig. 9, bonding pads, see page , 18, see page 22, face-to-face (F2F) mapping file is required between the two dies so that the bonding pads can be used as sources for the top die once the current has effectively crossed the bottom one….);
determining, by the processor, routing for the 3DIC, wherein the routing is determined based on the partial designs for the first chip and the second chip and further based on the two selections (see Fig. 4, die-by-die flow used for 3D-aware place and route, see page 19-20, A. netlist partitioning for 3D, the corresponding routing, is performed by the tool….); and
generating, by the processor, an updated design for the 3DIC including the first chip, the second chip, the first chip metal stack configuration, the second chip metal stack configuration, the bonding pitch, and the routing (see page, 17, In this paper we are building on this strategy last described to analyze new flow options at place and route (PNR) (e.g. different netlist partitioning), and to extend the 3D awareness beyond the PNR itself, into sign-off steps…...).
Regarding claims 2, 15, and 19, Giuliano discloses:
wherein the bonding pitch matches any of the first chip last metal level pitch and the second chip last metal level pitch (see Fig. 2-3, see Fig, 9, see page 17, col. 2 and page 18, [wherein the size of bonding-based pitches base on the interconnect technology and the requirement. Therefore, the ponding pitch can be match the first chip last metal level pitch and match the second chip top metal level pitch], see page 22).
Regarding claims 3, 15, and 19, Giuliano discloses:
wherein the bonding pitch is larger than any of the first chip last metal level pitch and the second chip last metal level pitch (see Fig. 2-3, see Fig, 9, see page 17, col. 2 and page 18, [wherein the size of bonding-based pitches base on the interconnect technology and the requirement. Therefore, the ponding pitch can be larger than the first chip last metal level pitch and larger than the second chip top metal level pitch], see page 22).
Regarding claims 4, 15, and 19, Giuliano discloses:
wherein the bonding pitch matches both the first chip last metal level pitch and the second chip last metal level pitch (see Fig. 2-3, see Fig, 9, see page 17, col. 2 and page 18, [wherein the size of bonding-based pitches base on the interconnect technology and the requirement. Therefore, the ponding pitch can be match the first chip last metal level pitch and match the second chip top metal level pitch], see page 22).
Regarding claim 5, Giuliano discloses:
wherein the first chip and the second chip have equal numbers of metal levels (see Fig. 9, top die and bottom die are equal numbers of metal levels).
Regarding claim 6, Giuliano discloses:
wherein the first chip metal levels are arranged in a first chip metal stack configuration, and wherein the second chip metal levels are arranged in a second chip metal stack configuration different from the first chip metal stack configuration (see Fig. 9 wherein the top die and second die have metal levels are arranged different in metal stack configuration, see first metal level …., see page 17, The design of Integrated Circuits (IC) is potentially affected by vertical stacking at different levels…).
Regarding claims 7, 16, and 20, Giuliano discloses:
wherein the first chip metal levels are arranged in a first chip metal stack configuration, and wherein the second chip metal levels are arranged in a second chip metal stack configuration that is the same as the first chip metal stack configuration (see see page 17, In 3D Stacked IC (3D-SIC) technology stand-alone dies are integrated with micro-bumps and TSVs. Both 3D-SIP and 3D-SIC use D2W based stacking, enabling different die sizes…., see page 19, The forking then occurs in the same die…).
Regarding claims 8, 16, and 20, Giuliano discloses:
wherein the first chip and the second chip have different numbers of metal levels, wherein the first chip metal levels are arranged in a first chip metal stack configuration, and wherein the second chip metal levels are arranged in a second chip metal stack configuration different from the first chip metal stack configuration (see page 17, In 3D Stacked IC (3D-SIC) technology stand-alone dies are integrated with micro-bumps and TSVs. Both 3D-SIP and 3D-SIC use D2W based stacking, enabling different die sizes….,).
Regarding claim 9, Giuliano discloses:
wherein the first chip includes a first chip substrate, wherein the second chip includes a second chip substrate, and wherein the first chip substrate and the second chip substrate have different layers (see Fig. 9, top die substrate and bottom die substrate, see page 17, In 3D Stacked IC (3D-SIC) technology stand-alone dies are integrated with micro-bumps and TSVs. Both 3D-SIP and 3D-SIC use D2W based stacking, enabling different die sizes….,).
Regarding claim 10, Giuliano discloses:
wherein the first chip substrate includes a first portion of a logic block, and wherein the second chip substrate includes a second portion of the logic block electrically connected to the first portion through the second chip metal levels, the first chip metal levels, and at least one of the bonding elements (see page 19, one top-level netlist to enclose the two dies together and specify their logical connectivity,….., page 21, For each block on the top die (e.g. memory macros) all the clock pins are identified and mapped to the corresponding Input/Output (IO) pins going to the bottom die (Figure 11)….).
Regarding claim 11, Giuliano discloses:
wherein the bonding elements include bumps associated with bump bonding (see page 17, In 3D Stacked IC (3D-SIC) technology stand-alone dies are integrated with micro-bumps….).
Regarding claim 12, Giuliano discloses:
wherein the bonding elements include pads (see Fig. 9, bonding pads).
Regarding claims 14 and 18, Giuliano discloses:
performing, by the processor, an analysis of any of power, performance, and area using the updated design for the 3DIC; determining, by the processor, whether the updated design for the 3DIC meets at least one power, performance, or area specification based on results of the analysis; and when the updated design for the 3DIC fails to meet the at least one power, performance, or area specification, iteratively repeating, by the processor, the determining of the first chip metal stack configuration, the second chip metal stack configuration, the bonding pitch, and the routing (see page 18, Given these 3D technology developments, the design flows and methodologies require careful verification and updates…, see page 19-20, power and timing analysis…., see Fig. 12 and 14, and page 22).
Conclusion
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/BRIAN NGO/ Primary Examiner, Art Unit 2851
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