Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group 1, Species B in the reply filed on 7/14/2026 is acknowledged.
Claims 1-20 are pending in the application. Claims 6, 13, and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 9 and 11 are rejected under 35 U.S.C. 102a1 as being anticipated by US20200075574A1 (Smith).
Regarding Claim 1, Smith discloses a semiconductor device (Fig. 8, el. 700,
Para. [0055]) comprising: a multi-stacked transistor structure (Fig. 8, Para. [0055]), comprising: a first stacked transistor structure comprising a first lower transistor device and a first upper transistor device (see annotated Fig. 8 below and Para. [0055]); and a second stacked transistor structure comprising a second lower transistor device, a second upper transistor device, and a third upper transistor device (see annotated Fig. 8 below and Para. [0055]).
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Regarding Claims 2 and 3, Smith discloses the semiconductor device of Claim 1, wherein the second and third upper transistor device comprise a first plurality of channel layers (see annotated Fig. 8 below), wherein each channel layer in the first plurality of channel layers is surrounded by one or more gate regions and at least one other structure (see annotated Fig. 8 below), wherein the at least one other structure comprises a first gate cut portion comprising dielectric material disposed between the second upper transistor device and the third upper transistor device (see annotated Fig. 8 below, Para. [0055] and Para. [0070]).
Regarding Claim 5, Smith discloses the semiconductor device of Claim 2, wherein the first lower transistor device, the first upper transistor device, and the second lower transistor device comprise a second plurality of channel layers, wherein each channel layer in the second plurality of channel layers is surrounded by one or more gate regions (see annotated Fig. 8 below).
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Claim 9 is rejected under 35 U.S.C. 102a1 as being anticipated by Smith.
Regarding Claim 9, Smith discloses a semiconductor device (Fig. 8, Para. [0055]) comprising: a first stacked transistor structure comprising a first lower transistor device and a first upper transistor device (see both annotated Fig. 8 above and Para. [0055]); and a second stacked transistor structure comprising a second lower transistor device, a second upper transistor device, and a third upper transistor device (see both annotated Fig. 8 above and Para. [0055]); wherein the second upper field-effect transistor; wherein the second upper field-effect transistor device and the third upper field-effect transistor device comprise a plurality of channel layers (see both annotated Fig. 8 above), each of the channel layers being surrounded by a first gate cut portion comprising dielectric material and one or more gate regions (see analysis of Claims 2-3).
Regarding Claim 11, Smith discloses the semiconductor device of Claim 9, wherein the first lower field-effect transistor device, the first upper field-effect transistor device, and the second lower field-effect transistor device comprise gate-all-around transistor devices (Fig. 8, which shows the gate side view of the device, with the gate wrapping all around the transistor devices).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Smith.
Regarding Claim 4, Smith discloses the semiconductor device of Claim 3.
Smith does not disclose a second gate cut portion comprising dielectric material disposed between the first stacked transistor structure and the second stacked transistor structure.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add a second gate cut portion comprising dielectric material between the first and second transistor stacks. This would have the benefit of allowing independent control of the first and second transistor stacks.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of US20220406715A1 (Xie).
Regarding Claim 7, Smith discloses the semiconductor device of Claim 1.
Smith does not disclose that the second stacked transistor comprises a first frontside source/drain contact for the second upper transistor device and a second frontside source/drain contact for the third upper transistor device.
Xie discloses a semiconductor device (Figs. 10B, el. 100) with a stacked transistor structure (para. [0033]) that has a frontside source/drain contact (Fig. 10B, el. 1030, Para. [0074]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add frontside source/drain contacts to the device of Smith. This has the advantage of allowing access to the source/drain from the top of the device (Para. [0092]).
Regarding Claim 8, Smith in view of Xie discloses the semiconductor device of Claim 7.
Smith in view of Xie does not disclose that the first frontside source/drain contact and the second frontside source/drain contact are connected to different signal lines.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to connect them to different signal lines. This would have the benefit of allowing more functionality in the circuit by having the S/D regions of the two transistors routed to different signals.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Smith.
Regarding Claim 12, Smith discloses the semiconductor device of Claim 9.
Smith does not disclose a second gate cut portion comprising dielectric material disposed between the first stacked transistor structure and the second stacked transistor structure.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add a second gate cut portion comprising dielectric material between the first and second transistor stacks. This would have the benefit of allowing independent control of the first and second transistor stacks.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Xie.
Regarding Claim 14, Smith discloses the semiconductor device of Claim 1.
Smith does not disclose that the second stacked transistor comprises a first frontside source/drain contact for the second upper transistor device and a second frontside source/drain contact for the third upper transistor device.
Xie discloses a semiconductor device (Figs. 10B, el. 100) with a stacked transistor structure (para. [0033]) that has a frontside source/drain contact (Fig. 10B, el. 1030, Para. [0074]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add frontside source/drain contacts to the device of Smith. This has the advantage of allowing access to the source/drain from the top of the device (Para. [0092]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Xie.
Regarding Claim 15, Smith in view of Xie discloses the semiconductor device of Claim 14.
Xie further discloses that the frontside source/drain contact is connected to a back end of the line signal line (see Xie, Claim 4).
Smith in view of Xie does not disclose that the first and second frontside source/drain contacts are connected to different back-end-of-line signal.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to connect them to different signal lines. This would have the benefit of allowing more functionality in the circuit by having the S/D regions of the two transistors routed to different signals.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 10, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination wherein at least one of the channel layers in the plurality of channel layers is surrounded by the one or more gate regions on three sides and the first gate cut portion on another side.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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