Prosecution Insights
Last updated: October 01, 2026
Application No. 18/586,767

SUPPORT SUBSTRATE, MANUFACTURING METHOD OF SUPPORT SUBSTRATE, AND MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE

Non-Final OA §102§103§112
Filed
Feb 26, 2024
Priority
Feb 28, 2023 — JP 2023-029939
Examiner
FAYETTE, NATHALIE RENEE
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
KIOXIA Corporation
OA Round
1 (Non-Final)
96%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 96% — above average
96%
Career Allowance Rate
48 granted / 50 resolved
+28.0% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
30 currently pending
Career history
77
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
51.4%
+11.4% vs TC avg
§102
26.4%
-13.6% vs TC avg
§112
19.1%
-20.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 50 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Election/Restrictions Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/06/2026. Claim Objections Claims 1-10 is/are objected to because of the following informalities: Claim 1 recites “conductivity” in Line L2 but should read –a first conductivity--. Claim 1 recites “conductivity” in Line L4 but should read –a second conductivity--. Claim 1 recites “conductivity” in Line L7 but should read –a third conductivity--. Claim 7 recites “the plurality of memory pillars are covered” in Line L6 but should read – the plurality of memory pillars is covered --. Claim 8 recites “conductivity” in Line L2 but should read –a first conductivity--. Claim 8 recites “conductivity” in Line L5 but should read –a second conductivity--. The balance of claims is objected to for being dependent upon an already objected claim. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 2, the limitation “the second layer is peeled off from the substrate by causing the second insulating layer to cleave by irradiation with laser light” in Lines L6-8, particularly pointing out and distinctly claiming the subject matter. The limitation “the second layer is peeled off from the substrate by causing the second insulating layer to cleave by irradiation with laser light” in Lines L6-8 is a process limitation, while the antecedent claim is a device claim. Claim 2 is then having both device and process limitation and fails to distinctly claim the subject matter. The balance of claims is rejected for being dependent upon an already rejected claim. Appropriate correction is required. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claims 2 and 3 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Regarding claim 2, claim 2 recites the process limitation “the second layer is peeled off from the substrate by causing the second insulating layer to cleave by irradiation with laser light” in Lines L6-8. Claim 2 depends of claim1, where claim 1 is a device claim with a listing of layers. Consequently, the device obtained in claim 2 has one layer less than the device in claim 1, so the device of claim 2 is broader in scope than the device in claim 1. Claim 2 has to specify a further limitation of the subject matter claimed and claim 2 fails to do so. Regarding claim 3, claim 3 is dependent of rejected claim 2 and is still missing one layer when compared to the device of claim 1, so claim 3 does not cure the deficiency of claim 2. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takagi et al. (US20210272898A1-Takagi98). Regarding claim 1, Takagi98 discloses a support substrate comprising: a substrate having conductivity (substrate 111/112/120/130 where 112/120/130 is a metal layer so having conductivity-[0082] [0083] [0084]); a first insulating layer disposed on the substrate (First insulating layer 110/140 [0079], [0086], Fig 4C, Fig 4D); a first layer having conductivity (First layer 112/120 being of metal material so having conductivity-Fig 5D, [0088]) and disposed on the first insulating layer (First layer 112/120 disposed on Insulating layer 110/140-Fig 5D); a second insulating layer disposed on the first layer (Second insulating layer 170 disposed on First layer 112/120-Fig 7A); a second layer having conductivity and disposed on the second insulating layer (second layer 172/120 being of metal material so having conductivity-[0103] [0106]); a plurality of first plugs penetrating the first insulating layer (First plugs 141/142 penetrating first insulating layer 140-Fig 5D) and connecting the substrate and the first layer (First plugs 141/142 connecting substrate 111/112/120/130 and first layer 112/120-Fig 5D); and a plurality of second plugs penetrating the second insulating layer (Second plugs 171 penetrating the Second insulating layer 170-Fig 9A) and connecting the first layer and the second layer (Second plugs 171 connecting first layer 112/120 and the second layer 172/120-Fig 8C). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takagi et al. (US20210272898A1-Takagi98) in view of Shimikawa et al. (US20200266089A1-Shimikawa89). Regarding claim 2, Takagi98 discloses all the elements of claim 1, as noted above. Takagi98 does not disclose a support substrate wherein the second layer serves as a base layer in which at least a part of a structure of a semiconductor device is formed at a time of manufacturing the semiconductor device, and the second layer is peeled off from the substrate by causing the second insulating layer to cleave by irradiation with laser light. Shimikawa89 teaches a support substrate wherein the second layer serves as a base layer (Second layer 15 serving as a base layer for interconnect layer 20-[0027] L1-7, Fig 1, Fig 2B, Fig 3B) in which at least a part of a structure of a semiconductor device is formed at a time of manufacturing the semiconductor device (Second layer 15 serving as a base layer for structure of semiconductor device 30 Left/Right mounted on interconnect layer 20-[0027] L1-7, [0029] L1-7, Fig 1, Fig 2B, Fig 3B), and the second layer is peeled off from the substrate by causing the second insulating layer to cleave (Second layer 15 peeled off from substrate 11 by causing second insulating layer 14 to cleave-[0036] L1-5, Fig 1, Fig 4B) by irradiation with laser light ([0039] L1-6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the support substrate of Takagi98 as taught by Shimikawa89 for the purpose of peeling the support substrate without damaging the support substrate and reducing the process cost (Shimikawa89: [0041]). Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takagi et al. (US20210272898A1-Takagi98) in view of Shimikawa et al. (US20200266089A1-Shimikawa89), and further in view of Theil et al. (US 20230197496 A1-Theil96). Regarding claim 3, Takagi98 and Shimikawa89 combination discloses all the elements of claim 2, as noted above. Takagi98 and Shimikawa89 combination does not teach a support substrate wherein a layer thickness of the first insulating layer is less than or equal to 100 nm, and a layer thickness of the second insulating layer is more than or equal to 300 nm. Theil96 teaches a support substrate wherein a layer thickness of the first insulating layer is less than or equal to 100 nm (first insulating layer 14 thickness being in a range of 50 nm to 500 nm, so 50nm being less than 100 nm-[0039]L20-30), and a layer thickness of the second insulating layer is more than or equal to 300 nm (Second insulating layer 16 thickness being in the range between 500nm and 1µm, with 500 nm being more than or equal to 300 nm-[0042] L1-10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the support substrate of Takagi98 in view of Shimikawa89 as taught by Theil96 for the purpose of being robust enough to withstand the desired processing of the temporarily bonded structure (Theil96: [0043]). Claim(s) 4, 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takagi et al. (US20210272898A1-Takagi98) in view of Baraskar et al. (US 20210082865 A1-Baraskar65). Regarding claim 4, Takagi98 discloses all the elements of claim 1, as noted above. Takagi98 does not disclose a support substrate comprising on the second layer, a plurality of memory pillars connected to the second layer. Baraskar65 teaches a support substrate comprising on the second layer, a plurality of memory pillars connected to the second layer (on the second layer 10, a plurality of memory pillars 58 connected to the second layer 10-Fig 13A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the support substrate of Takagi98 as taught by Baraskar65 for the purpose of providing lower cost carrier and handle substrates used in a bonded assembly so reducing the cost of the fabricated device (Baraskar65: [0244]). Regarding claim 6, Takagi98 and Baraskar65 combination discloses all the elements of claim 4, as noted above. Takagi98 further discloses a support substrate comprising wherein an arrangement density of the plurality of first plugs in the first insulating layer (First plugs 141/142 penetrating first insulating layer 140 having a density higher than Second plugs 171 density in Second insulating layer 170-Fig 9A , Fig 5D) is higher than an arrangement density of the plurality of second plugs in the second insulating layer. Regarding claim 7, Takagi98 and Baraskar65 combination discloses all the elements of claim 4, as noted above. Baraskar65 further teaches a support substrate comprising a peripheral circuit disposed on a semiconductor substrate (peripheral circuit 710/780 disposed on semiconductor substrate 708-Fig 15), and covered with a third insulating layer (peripheral circuit 710/780 covered with third insulating layer 760-Fig 15), wherein the plurality of memory pillars are covered with a fourth insulating layer (memory pillars 58 covered by fourth insulating layer 65-Fig 15), and the semiconductor substrate and the substrate are bonded at the third insulating layer and the fourth insulating layer (Semiconductor substrate 708 bonded at third layer 760, substrate 9 bonded at fourth insulating layer 65-Fig 15). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the support substrate of Takagi98 as taught by Baraskar65 for the purpose of providing lower cost carriers and handle substrates used in a bonded assembly so reducing the cost of the fabricated device (Baraskar65: [0244]). Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takagi et al. (US20210272898A1-Takagi98) in view of Baraskar et al. (US 20210082865 A1-Baraskar65), and further in view of Theil et al. (US 20230197496 A1-Theil96). Regarding claim 5, Takagi98 and Baraskar65 combination discloses all the elements of claim 4, as noted above. Takagi98 and Baraskar65 combination does not disclose a support substrate wherein a layer thickness of the second layer is within a range between 300 nm and 700 nm. Theil96 teaches a support substrate wherein a layer thickness of the second layer is within a range between 300 nm and 700 nm (Second insulating layer 16 thickness being in the range between 500nm and 1µm, with 500 nm being within a range between 300 nm and 700 nm-[0042] L1-10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the support substrate of Takagi98 in view of Baraskar65 , as taught by Theil96, for the purpose of being robust enough to withstand the desired processing of the temporarily bonded structure (Theil96: [0043]). Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takagi et al. (US20210272898A1-Takagi98) in view of Theil et al. (US 20230197496 A1-Theil96). Regarding claim 5, Takagi98 discloses all the elements of claim 4, as noted above. Takagi98 does not disclose a support substrate wherein a layer thickness of the second layer is within a range between 300 nm and 700 nm. Theil96 teaches a support substrate wherein a layer thickness of the second layer is within a range between 300 nm and 700 nm (Second insulating layer 16 thickness being in the range between 500nm and 1µm, with 500 nm being within a range between 300 nm and 700 nm-[0042] L1-10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the support substrate of Takagi98 as taught by Theil96, for the purpose of being robust enough to withstand the desired processing of the temporarily bonded structure (Theil96: [0043]). Regarding claim 8, Takagi98 discloses a support substrate comprising: a substrate having conductivity (substrate 111/112/120/130 where 112/120/130 is a metal layer so having conductivity-[0082] [0083] [0084]); a first insulating layer disposed on the substrate (First insulating layer 110/140 [0079], [0086], Fig 4C, Fig 4D); a first layer having conductivity (First layer 112/120 being of metal material so having conductivity-Fig 5D, [0088]) and disposed on the first insulating layer (First layer 112/120 disposed on Insulating layer 110/140-Fig 5D); and a plurality of first plugs penetrating the first insulating layer (First plugs 141/142 penetrating first insulating layer 140-Fig 5D) and connecting the substrate and the first layer (First plugs 141/142 connecting substrate 111/112/120/130 and first layer 112/120-Fig 5D) Takagi98 does not disclose a support substrate a first insulating layer having a layer thickness of less than or equal to 100 nm. Theil96 teaches a support substrate a first insulating layer having a layer thickness of less than or equal to 100 nm (first insulating layer 14 thickness being in a range of 50 nm to 500 nm, so 50nm being less than 100 nm-[0039] L20-30). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the support substrate of Takagi98 in view of Shimikawa89 as taught by Theil96 for the purpose of being robust enough to withstand the desired processing of the temporarily bonded structure (Theil96: [0043]). Regarding claim 9, Takagi98 and Theil96 combination discloses all the elements of claim 8, as noted above. Takagi98 further discloses a support substrate wherein an area of the plurality of first plugs is greater than or equal to 50% of an area of an arrangement region of the first insulating layer when viewed from a stacking direction of the first insulating layer and the first layer (Area of first plugs 141/142 in dashed gray, is at least 50% of the area of the arrangement region of the first insulating layer in white as viewed in the staking direction in the stacking direction/vertical direction-Examiner's annotated Fig 5D). PNG media_image1.png 497 824 media_image1.png Greyscale Regarding claim 10, Takagi98 and Theil96 combination discloses all the elements of claim 8, as noted above. Takagi98 further discloses a support substrate wherein each of the plurality of first plugs has at least one of a columnar shape, a line shape, or an annular shape (First plugs 141/142 being a column so having a line shape-Examiner's annotated Fig 5D). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Okandan et al. (US8729673B1-Okandan73) teaches a support substrate with a plurality of plugs (line shape plugs 42-Fig 4A). Zhou et al. (US10910272B1-Zhou72) teaches a support substrate (reusable support substrate-Title) with a plurality of plugs (line shape plugs 5-Fig 2A). Wimplinger et al. (US 20250153481 A1-Wimplinger81) teaches a support substrate (support substrate 1-Fig 2C) with a plurality of plugs (line shape plugs 5-Fig 2C), with irradiation with laser light (Fig 3d, Fig 3e). Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. NATHALIE R. FAYETTE Examiner Art Unit 2812 /NATHALIE R FAYETTE/Examiner, Art Unit 2812 08/28/2026 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Feb 26, 2024
Application Filed
Sep 15, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751261
SELECTIVE DEPOSITION USING GRAPHENE AS AN INHIBITOR
3y 9m to grant Granted Sep 29, 2026
Patent 12745442
TRANSISTOR BACKSIDE ROUTING LAYERS WITH CONTACTS HAVING VARYING DEPTHS
4y 5m to grant Granted Sep 22, 2026
Patent 12745394
THREE-DIMENSIONAL MEMORY AND MANUFACTURING METHOD THEREOF
3y 8m to grant Granted Sep 22, 2026
Patent 12740105
FABRICATING OF A QUANTUM DEVICE WITH AUTOALIGNMENT OF THE GATES ON THEIR RESPECTIVE ACTIVE ZONE REGION
3y 9m to grant Granted Sep 15, 2026
Patent 12733196
HfS3 FIELD-EFFECT TRANSISTORS WITH A TWO-DIMENSIONAL HOLE GAS
2y 10m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
96%
Grant Probability
99%
With Interview (+5.7%)
3y 3m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 50 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month