DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The status of the claims is as follows: Claims 1-20 are pending in the application.
Claims 11-20 are withdrawn. An action on the merits for claims 1-10 follows.
Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)- (d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non- English application.
IDS
All references provided in the IDS have been considered.
Election/Restrictions
Applicant’s election without traverse of Species I (corresponding to claims 1-10) in the reply filed on 07/08/2026 is acknowledged. Accordingly, claims 11-20, reading on non-elected Species II, have been withdrawn from consideration at this time.
Specification
The disclosure is objected to because of the following informalities:
The element labelled “HD” from Fig. 6 does not appear to be described in the specification.
Appropriate correction is required.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Semiconductor Memory Device Comprising Heat Crystallized Material.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yanai et al. (US 20210273055 A1), hereinafter Yanai.
Regarding Claim 10, Yanai teaches a semiconductor memory device ("memory cell array," (1); Figs. 1 (schematic perspective view), 2 (schematic sectional view), Paragraph [0013]) comprising:
a stacked body ("stacked body," (100); Fig. 1, Paragraph [0015]) formed by alternately stacking, in a first direction ("Z-direction," (Z); Figs. 1, 2, Paragraph [0016]), a plurality of first insulating layers ("insulating layer," (72); Fig. 2, Paragraph [0029]) and a plurality of first conductive layers ("electrode layer," (70); Fig. 2, Paragraph [0028]) each of the plurality of first insulating layers (72) and the plurality of first conductive layers (70) functions as a control gate ("control gate," (CG); Paragraph [0040]) of a memory cell transistor ("transistors," (STD, STS); Fig. 1, Paragraph [0027]);
a source line ("source line," (SL); Fig. 2, Paragraph [0021]) disposed on one side of the stacked body (100) in the first direction (Z), the source line (SL) comprising a semiconductor layer ("semiconductor layer," (12); Fig. 2, Paragraph [0022]); and
a first columnar body ("columnar parts," (CL); Fig. 2, Paragraph [0030]) extending in the first direction (Z) in the stacked body (100), an end of the first columnar body (CL) reaching an inside of the semiconductor layer (12), the first columnar body (CL) comprising a first semiconductor portion ("semiconductor body," (20); Fig. 2, Paragraph [0032]), wherein
a first conductive type impurity concentration of the first semiconductor portion (20) is 1 × 1020 cm-3 or higher ("for example, 1020 to 1021/cm3;" Paragraph [0054]) in at least a part of an area ("lower region," (20a); Fig. 2, Paragraph [0034]) located in the semiconductor layer (12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yanai in view of Okawa et al. (US 20190287986 A1), hereinafter Okawa.
Regarding Claim 1, Yanai teaches a semiconductor memory device ("memory cell array," (1); Figs. 1 (schematic perspective view), 2 (schematic sectional view), Paragraph [0013]), comprising:
a stacked body ("stacked body," (100); Fig. 1, Paragraph [0015]) formed by alternately stacking, in a first direction ("Z-direction," (Z); Figs. 1, 2, Paragraph [0016]), a plurality of first insulating layers ("insulating layer," (72); Fig. 2, Paragraph [0029]) and a plurality of first conductive layers ("electrode layer," (70); Fig. 2, Paragraph [0028]), each of which functions as a control gate ("control gate," (CG); Paragraph [0040]) of a memory cell transistor ("transistors," (STD, STS); Fig. 1, Paragraph [0027]);
a first columnar body (first "columnar parts," (CL); Fig. 2, Paragraph [0030]) extending in the first direction (Z) in the stacked body (100), the first columnar body (first CL) comprising a first semiconductor portion (first "semiconductor body," (20); Fig. 2, Paragraph [0032]);
an insulating film (“insulating layer,” (44); Figs. 1, 2, Paragraph [0024]) disposed at an end portion of the semiconductor memory device (1); and
a second columnar body (second "columnar parts," (CL); Fig. 2, Paragraph [0030]) extending in the first direction (Z) in the insulating film (44), the second columnar body (second CL) comprising a second semiconductor portion (second "semiconductor body," (20); Fig. 2, Paragraph [0032]), wherein
an impurity concentration of the second semiconductor portion (second 20) at a bottom portion (“lower region,” (20a); Fig. 2, Paragraph [0034]) of the second columnar body (second CL) is higher (“impurity concentration of the lower region 20a is higher than that of the upper region 20b;” Paragraph [0052]) than an impurity concentration of the first semiconductor portion (first 20) at an intersection portion (“upper region,” (20b); Fig. 2, Paragraph [0036]) between the first columnar body (first CL) and the first conductive layer (70).
Yanai does not explicitly teach the second semiconductor portion shorter than the first semiconductor portion in the first direction,
Okawa teaches at least a semiconductor memory device (“memory device,” (1); Fig. 1A, Paragraph [0019]) comprising:
the second semiconductor portion (“semiconductor layer,” (33); Paragraph [0022]) shorter than the first semiconductor portion (“semiconductor layer,” (30); Paragraph [0030]) in the first direction (“Z-direction,” (Z); Paragraph [0020]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Yanai with the teachings of Okawa such that the second semiconductor portion is shorter than the first semiconductor portion in the first direction. Altering the length of the semiconductor portions within memory holes allows the shorter semiconductor layer to be disposed away from a source line with the added benefit of being electrically insulated from the source line (Paragraphs [0022, 0023]).
Regarding Claim 3, Yanai as modified by Okawa teaches the semiconductor memory device (Yanai, 1) according to claim 1, wherein the impurity concentration of the second semiconductor portion (second 20) at the bottom portion (second 20a) of the second columnar body (second CL) is higher than the impurity concentration (“the impurity concentration of the lower region 20a is higher than the impurity concentration of the upper region 20b;” Paragraph [0054]) of the second semiconductor portion (second 20) at a first portion (second 20b) different from the bottom portion (second 20a) of the second columnar body (second CL).
Regarding Claim 4, Yanai as modified by Okawa teaches the semiconductor memory device (Yanai, 1) according to claim 3, wherein the impurity concentration at the first portion (second 20b) of the second columnar body (second CL) is equal to the impurity concentration of the first semiconductor portion (first 20) at the intersection portion (first 20b) of the first columnar body (first CL). (Note: the structure and impurity concentrations of the two columnar bodies shown in Yanai are the same across each 20a and each 20b; Paragraph [0032, 0054])
Regarding Claim 5, Yanai as modified by Okawa teaches the semiconductor memory device (Yanai, 1) according to claim 1, wherein the impurity concentration of the second semiconductor portion (second 20) at the bottom portion (second 20a) of the second columnar body is 1 × 1020 cm-3 or higher (“for example, 1017 to 1019/cm3).
Regarding Claim 6, Yanai as modified by Okawa teaches the semiconductor memory device (Yanai, 1) according to claim 5, wherein the impurity concentration of the first semiconductor portion (first 20) at the intersection portion (first 20b) between the first columnar body (first CL) and the first conductive layer (70) is 5 × 1019 cm-3 or lower (“for example, 1017 to 1019/cm3;” Paragraph [0054]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yanai in view of Okawa and further in view of Li et al. (US 20220310643 A1), hereinafter Li.
Regarding Claim 2, Yanai as modified by Okawa teaches the semiconductor memory device according to claim 1.
Yanai as modified by Okawa does not explicitly teach wherein the first and second semiconductor portions include a polysilicon film, and a particle diameter of a crystal of the polysilicon film is 80 nm or more.
Li teaches a semiconductor memory device (“3D memory device,” (100); Fig. 1, Paragraph [0031]) wherein the first and second semiconductor portions (“semiconductor channel,” (116); Fig. 1, Paragraph [0036]) include a polysilicon film (“includes […] polysilicon;” Paragraph [0036]), and a particle diameter of a crystal of the polysilicon film is 80 nm or more (“the grain size […] can range from 100nm to 600nm;” Paragraph [0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Yanai as modified by Okawa with the teachings of Li such that the semiconductor portion comprises polysilicon film where a particle diameter of a crystal is 80 nm or more. The increased grain size effectively increases carrier mobility with added benefit of increasing device speed (Paragraph [0036]).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (US 20220068967 A1), hereinafter Yamazaki in view of Okajima (US 20210313340 A1), hereinafter Okajima.
Regarding Claim 7, Yamazaki teaches at least a semiconductor memory device (“memory cell array,” (700); Figs. 1A-3B, Paragraph [0104]) comprising:
a stacked body (701, 722) formed by alternately stacking a plurality of first insulating layers (“insulators,” (722); Paragraph [0104]) and a plurality of first conductive layers (“conductors,” (701); Paragraph [0104]) in a first direction (“z-axis,” (z); Fig. 1, Paragraph [0104]; and
a columnar body (“opening portion,” comprising 703, 704, 711, 712; Fig. 1, Paragraph [0105]) comprising a first semiconductor portion (“oxide semiconductor,” (704); Fig. 3A, Paragraph [0136]) and a second insulator portion (“insulator,” (703); Paragraph [0127]) disposed between the first semiconductor portion (704) and the stacked body (701, 722), wherein
an intersection portion (“memory transistor,” (MT); Fig. 2B, Paragraph [0104]) between the plurality of first conductive layers (701) and the first semiconductor portion (704) functions as a transistor (“transistor;” Paragraph [0104]), and a first conductive type impurity concentration (“impurity concentration;” Paragraph [0234]) at the intersection portion (MT).
Yamazaki does not explicitly teach wherein the impurity concentration of the first semiconductor portion is 1 × 1020 cm-3 or higher.
Okajima teaches at least a semiconductor memory device (“memory cell array,” (10); Fig. 15, Paragraph [0018, 0164]) wherein an impurity concentration (“n-type impurity;” Paragraph [0165]) of the first semiconductor portion (“semiconductor;” (36); Paragraph [0165]) is 1 × 1020 cm-3 or higher (“1E20/cm3 or more;” Paragraph [0165]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Yamazaki with the teachings of Okajima such that the impurity concentration of the first semiconductor portion is 1 × 1020 cm-3 or higher. This is because the semiconductor has a high n-type impurity concentration that may affect the thickness of the semiconductor portion (Paragraph [0165]) for the benefit of suppressing an increase in sizer of the memory cell array (Paragraph [0170]).
Regarding Claim 8, Yamazaki as modified by Okajima teaches the semiconductor memory device according to claim 7, wherein a carrier concentration (“carrier concentration;” Paragraph [0234]) of the first semiconductor portion (704) is lower than the impurity concentration (“reduce the carrier concentration of the metal oxide film […] lower than1x1012cm-3;” Paragraph [0234]).
Regarding Claim 9, Yamazaki as modified by Okajima teaches the semiconductor memory device according to claim 7, wherein the first semiconductor portion (704) includes an n-type impurity (“metal oxide becomes n-type;” Paragraph [0241]), and
a concentration of a mobile electron (“carrier concentration;” Paragraph [0234]) of the first semiconductor portion (704) is lower than a concentration of the n-type impurity (“reduce the carrier concentration of the metal oxide film […] lower than1x1012cm-3;” Paragraph [0234]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nolan Stuessy whose telephone number is (571) 645-5843. The examiner can normally be reached on M-F; 9:00-5:00 (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NOLAN GABRIEL STUESSY/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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