Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim(s) 21-40 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Information Disclosure Statement
The information disclosure statements filed 2/24/26; 4/21/26 have been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 32-36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pagaila (U.S. Patent Publication No. 2012/0049388).
Referring to figures 6-7, Pagaila teaches a subpanel, comprising:
a plurality of semiconductor dies (124), wherein each semiconductor die (124) comprises a semiconductor die top side, a semiconductor die bottom side, and one or more semiconductor die lateral sides between the semiconductor die top side and the semiconductor die top side (see figure 6a);
an encapsulant (174) comprising an encapsulant top outer surface, an encapsulant bottom outer surface, and one or more encapsulant lateral outer surface between the encapsulant top side and the encapsulant bottom outer surface, wherein the encapsulant (174) laterally surrounds the one or more semiconductor die (124) lateral sides of each semiconductor die and exposes the semiconductor die top side of each semiconductor die at the encapsulant top outer surface (see figure 6c); and
one or more layers of material (176) covering at least a portion of the encapsulant top outer surface (174), at least a portion of the semiconductor die (124) top outer surface of each semiconductor die, and at least one a portion of a first encapsulant outer lateral outer surface of the one or more encapsulant lateral outer surfaces (174, see figures 6-7).
Regarding to claim 33, the subpanel is circular (see figure 3a).
Regarding to claim 34, the one or more layers of material include a dielectric layer (180, see figures 6d-6e).
Regarding to claim 35, the dielectric layer (180) contacts the first encapsulant lateral outer surface (174, see figure 6d).
Regarding to claim 36, the one or more layers of material include a conductive layer (178, 182, see figures 6-7).
Regarding to claim 37, the conductive layer does not extend along the first encapsulant lateral outer surface (see figures 4-10).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 38-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pagaila (U.S. Patent Publication No. 2012/0049388) applied in claim(s) 32-37 above in view of Woodard et al. (U.S. Patent Publication No. 2012/0080832).
Pagaila (U.S. Patent Publication No. 2012/0049388).
Referring to figures 6-7, Pagaila teaches a subpanel, comprising:
a plurality of semiconductor dies (124), wherein each semiconductor die (124) comprises a semiconductor die top side, a semiconductor die bottom side, and one or more semiconductor die lateral sides between the semiconductor die top side and the semiconductor die top side (see figure 6a);
an encapsulant (174) comprising an encapsulant top outer surface, an encapsulant bottom outer surface, and one or more encapsulant lateral outer surface between the encapsulant top side and the encapsulant bottom outer surface, wherein the encapsulant (174) laterally surrounds the one or more semiconductor die (124) lateral sides of each semiconductor die and exposes the semiconductor die top side of each semiconductor die at the encapsulant top outer surface (see figure 6c); and
one or more layers of material (176) covering at least a portion of the encapsulant top outer surface (174), at least a portion of the semiconductor die (124) top outer surface of each semiconductor die, and at least one a portion of a first encapsulant outer lateral outer surface of the one or more encapsulant lateral outer surfaces (174, see figures 6-7).
However, the reference does not clearly teach upper/lower chamfer subpanel (in claims 38-40).
Woodard et al. teaches a device having an upper/lower chamfer subpanel (see figures 21-23, meeting claims 38-40).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the invention was filed would form a device having an upper/lower chamfer subpanel in Pagaila as taught by Woodard et al. because it is known in the art to increase yield and total die per wafer.
Allowable Subject Matter
Claims 21-31 are allowed. None of the reference teaches/suggests a gap separates a subpanel lateral side of the first subpanel from a subpanel lateral side of the second subpanel; and one or more layers of material over the subpanel top side of the first subpanel, a portion of the panel top side that corresponds to the gap separating the first subpanel and the second subpanel, and the subpanel top side of the second subpanel.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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