DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-11 & 18-21, in the reply filed on Dec. 29, 2025 is acknowledged.
Claims 12-17 and 22-30 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on Dec. 29, 2025.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tekumalla et al (US Patent 8,826,087).
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Regarding claim 1, Tekumalla et al disclose [see Figs. 1-3 above] A circuit (system 100) comprising: a circuit core (tester 102) configured to perform an operational function (testing); scan-chain registers (scan chain 204) configured to propagate a set of system-on-chip (SoC) scan data [via scan data 110] that is generated from an automatic test pattern generator (ATPG) (test pattern generator 112) [see col. 3, lines 7-8] input to the circuit to set a different device state of the circuit core (102) at each shift of the SoC scan data (110); and a plurality of bidirectional input/output (I/O) circuits (input/output circuitry 202-1, 202-2 and 202-3) [see col. 5, lines 41-46] each comprising a bidirectional I/O control, an I/O pad, and testing logic, the testing logic being configured to alternately facilitate input parametric testing and output parametric testing of the respective I/O pad via the respective bidirectional I/O control at each shift of the set of SoC scan data (110).
Regarding claim 11, Tekumalla et al disclose a plurality of multiplexers (multiplexer 302) configured to switch each input of the bidirectional I/O control of each of the bidirectional I/O circuits (202-1, 202-2 and 202-3) from the circuit core (102) to the testing logic in response to a test enable signal [see col. 6, lines 52-57 and col. 7, lines 4-16 for details].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 for details.
Allowable Subject Matter
Claims 2-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: regarding claim 2, the primary reason for the allowance of the claim is due to a power terminal, wherein the testing logic is configured to facilitate a quiescent current measurement test of the power terminal concurrently with each of the input and output parametric testing of the respective I/O pad of each of the bidirectional I/O circuits at each shift of the set of SoC scan data via a digital power supply (DPS).
Regarding claim 3, the primary reason for the allowance of the claim is due to the testing logic comprises a sense and drive-back network coupled between an input and an output of the bidirectional I/O control of the respective one of the bidirectional I/O circuit, the sense and drive-back network being configured to alternate between providing a output data signal to the input of the respective bidirectional I/O control to provide the output data signal to the I/O pad in the output parametric testing, and receiving an input data signal provided at the I/O pad from the output of the respective bidirectional I/O control to the sense and drive-back network in the input parametric testing. Since claim 4 depends from claim 3, it also has allowable subject matter.
Regarding claim 5, the primary reason for the allowance of the claim is due to a bidirectional switching control network configured to alternately set the bidirectional I/O control of each of the bidirectional I/O circuits to an input mode and an output mode at each shift phase or shift and capture phase of the set of SoC scan data in response to a scan enable signal and a scan clock signal that are each associated with propagating the SoC scan data. Since claims 6-10 depend from claim 5, they also have allowable subject matter.
Regarding claim 18, the primary reason for the allowance of the claim is due to a circuit comprising, in combination with other limitations, the testing logic being configured to facilitate input and output parametric testing of the I/O pad via the respective bidirectional I/O control by a pin parametric measurement unit (PPMU) concurrently with a quiescent current measurement test of the power terminal by a digital power supply (DPS) at each shift of the set of SoC scan data. Since claims 19-21 depends from claim 18, they also have allowable subject matter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERMELE M HOLLINGTON whose telephone number is (571)272-1960. The examiner can normally be reached Mon-Fri 7:00am-3:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee E Rodak can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JERMELE M HOLLINGTON/ Primary Examiner, Art Unit 2858