DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to Arguments
Applicant's arguments filed July 15, 2026, have been fully considered but they are not persuasive.
a)Regarding claim 1, the applicants states: “…Tekumalla, however, clearly teaches, and shows in FIG. 2, that scan chain 204 is located within IC 104 and NOT tester 102…Tekumalla clearly teaches that tester 102 and IC (integrated circuit) 104 are physically separated from each other with tester 102 being electrically coupled to IC 104. Examiner, however, combines both into a single circuit "(system 100)". Applicant believes Examiner did this to give him the best chance of trying to meeting all of the limitations Claim 1. However, now that Examiner has combined into "a single circuit (system 100)", Examiner cannot avoid the negative consequences of making this combination. More specifically, if tester 102 and IC 104 form part of the same "circuit", it is not possible that Tekumalla under Examiner's determination teaches, "scan-chain registers configured to propagate a set of system-on-chip (SoC) scan data that is generated from an automatic test pattern generator (ATPG) input to the circuit..”, as the automatic test pattern generator (ATPG) under Examiner's determination is actually part of "the circuit", and cannot therefore "input to the circuit" scan data generated from the ATPG into the circuit as the ATPG is already part of "the circuit" under Examiner's determination. As such, Tekumalla, under Examiner's determination, fails to teach or suggest, "scan-chain registers configured to propagate a set of system-on-chip (SoC) scan data that is generated from an automatic test pattern generator (ATPG) input to the circuit to set a different device state of the circuit core at each shift of the SoC scan data", as required by Claim 1. Examiner's determination is supposition not supported by fact which is little more than improper hindsight reconsideration which must be withdrawn. Accordingly, for this reason alone, the 35 U.S.C. 102(a)(1) rejection of Claim 1 is improper and must be withdrawn…”
In response to the above, the examiner respectfully disagrees. First, the examiner would like to remind the applicants that the definition of “circuit” in engineering means to have a closed loop path of electrical components through which electric current flows to perform a defined function. The examiner also would like to point in Tekumalla it states: “FIG. 1 shows an embodiment of the invention in which a testing system 100 comprises a tester 102 and an integrated circuit under test 104…[col. 2, lines 61-63]” Also in col. 3, lines 2-6: “…In other embodiments, at least a portion of the tester 102, such as the test pattern generator 112, may be incorporated into the integrated circuit 104. Alternatively, the entire tester 102 may be incorporated into the integrated circuit 104, as in a built-in self-test (BIST) arrangement.” With col. 3, lines 2-6 stated above, it clearly described that the entire tester 102 maybe incorporated into IC 104 to make up only one circuit to operate as a built-in self-test (BIST) circuit. Hence, the examiner did not used improper hindsight, provided facts and has shown “each and every element as set forth in the claims be found, either expressly or inherently described, in a single prior art patent." Verdegall Bros. V. Union Oil Co. of California, 2 USPQ2d 1051, 1053 (Fed. Cir. 1987). See also, Richardson V. Suzuki Motor Co., 9 USPQ2d 1913, 1920 (Fed. Cir. 1989). Therefore, the examine maintains that Tekumalla teaches “"scan-chain registers configured to propagate a set of system-on-chip (SoC) scan data that is generated from an automatic test pattern generator (ATPG) input to the circuit...”
B) The applicants further argues: “…Examiner, however, does not identify by reference number or location in Tekumalla's specification what can be considered "an I/O pad" in each of input/output circuitry 202-1, 202-2 and 202-3. As such, Tekumalla fails to teach or suggest, "a plurality of bidirectional input/output (I/O) circuits each comprising a bidirectional I/O control, an I/O pad, and testing logic…”
In response to the above, the examiner respectfully disagrees. In col. 5, lines 41-46 of the prior art, it states: “The input-output circuitry 202-1, 202-2 and 202-3 as illustrated comprises respective output enable (OE) circuitry 206-1, 206-2 and 206-3. Each instance of the OE circuitry 206 comprises one or more OE control signal lines that are used to configure a corresponding bidirectional signal pad of the associated instance of the input-output circuitry 202…” The bidirectional signal pad above is the equivalent of the claimed I/O pad. Therefore, the examiner maintains that the prior art still teaches the claimed invention as also shown below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tekumalla et al (US Patent 8,826,087).
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Regarding claim 1, Tekumalla et al disclose [see Figs. 1-3 above] A circuit (system 100) comprising: a circuit core (tester 102) configured to perform an operational function (testing); scan-chain registers (scan chain 204) configured to propagate a set of system-on-chip (SoC) scan data [via scan data 110] that is generated from an automatic test pattern generator (ATPG) (test pattern generator 112) [see col. 3, lines 7-8] input to the circuit to set a different device state of the circuit core (102) at each shift of the SoC scan data (110); and a plurality of bidirectional input/output (I/O) circuits (input/output circuitry 202-1, 202-2 and 202-3) [see col. 5, lines 41-46] each comprising a bidirectional I/O control, an I/O pad, and testing logic, the testing logic being configured to alternately facilitate input parametric testing and output parametric testing of the respective I/O pad via the respective bidirectional I/O control at each shift of the set of SoC scan data (110).
Regarding claim 11, Tekumalla et al disclose a plurality of multiplexers (multiplexer 302) configured to switch each input of the bidirectional I/O control of each of the bidirectional I/O circuits (202-1, 202-2 and 202-3) from the circuit core (102) to the testing logic in response to a test enable signal [see col. 6, lines 52-57 and col. 7, lines 4-16 for details].
Conclusion
Allowable Subject Matter
Claims 2-10 and 18-21 are allowed over the prior art.
The following is a statement of reasons for the indication of allowable subject matter: regarding claims 2,-3, 5, the reason for the allowance of the claims are due to amending the dependent claims into independent claims based on the allowable subject matter presented by the examiner in the Office Action mailed on January 15, 2026. Since claims 4 depends from claim 3 and claims 6-10 depend from claim 5, they also have allowable subject matter.
Regarding claim 18, the reason for the allowance of the claim was presented by the examiner in the Office Action mailed on January 15, 2026.
Based on the examiner maintaining the rejection to claims 1 and 11 above, the following is being applied.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERMELE M HOLLINGTON whose telephone number is (571)272-1960. The examiner can normally be reached Mon-Fri 7:00am-3:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee E Rodak can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JERMELE M HOLLINGTON/ Primary Examiner, Art Unit 2858
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