DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1 – 3, 5 - 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (9324574).
With regard to claim 1, Kang discloses a method (for example, see figs. 1, 3A – 3M) of manufacturing a semiconductor device, the method comprising:
forming an etch target layer (layers 101, 100 function as an etch target layer) within a cell region comprising a cell center region (CELL REGION as shown in figs. 1, 3L) and a cell edge region (a peripheral region PC, as shown in figs. 1, 3L functions as a cell edge region) surrounding the cell center region;
forming an edge mask pattern (referred to as “110P1” by examiner’s annotation shown in fig. 3L below; wherein an edge mask pattern 110P1 is a portion of the hard mark pattern 110P) on (above or directly and indirectly on) an entire surface of the cell edge region (the peripheral region PC), on the etch target layer (layers 101, 100 function as the etch target layer), and forming a plurality of center mask patterns (referred to as “110P2” by examiner’s annotation shown in fig. 3L below; wherein center mask patterns 110P2 are portions of the hard mark pattern 110P) spaced apart from each other on the cell center region (CELL REGION as shown in fig. 3L) through a quadruple patterning process (four patterning process including, for example, first patterning process as shown in figs. 3A – 3B, a second patterning process as shown in fig. 3F-3G, a third patterning process as shown in fig. 3H-3I, a four patterning process as shown in fig. 3K-3L); and
forming a first etch pattern (referred to as “100P1” by examiner’s annotation shown in fig. 3M below; wherein a first etch pattern 100P1 is a portion of the layer 100) on the cell edge region (the peripheral region PC), and forming a plurality of second etch patterns (referred to as “100P2” by examiner’s annotation shown in fig. 3M below; wherein the second etch patterns 100P2 are portions of the layer 100P) spaced apart from each other on the cell center region (CELL REGION as shown in fig. 3M) by etching the etch target layer (the etch target portion 100 of the etch target layer 100, 101) using the edge mask pattern (110P1 as shown in fig. 3L below) and the plurality of center mask patterns (110P2 as shown in fig. 3L below) as etch masks,
wherein the first etch pattern (100P1) and the plurality of second etch patterns (100P2) are formed as active patterns (for example, see column 5, lines 42 – 44) respectively in the cell edge region (PC) and the cell center region (CELL REGION).
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With regard to claim 2, Kang discloses a width (referred to as “X1” by examiner’s annotation shown in fig. 3L below) of the edge mask pattern (110P1) is larger than a width (referred to as “X2” by examiner’s annotation shown in fig. 3L below) of each of the plurality of second etch patterns (100P2) in a cross section.
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With regard to claim 3, Kang discloses the etch target layer (layers 101, 100 function as an etch target layer) functions as a semiconductor substrate.
With regard to claim 5, Kang discloses the edge mask pattern (110P1, fig. 3L above) and the plurality of center mask patterns (110P2, fig. 3L above) are formed as hard mask patterns.
With regard to claim 6, Kang discloses a peripheral circuit region (region SL, PC functioning as a peripheral circuit region) is around the cell region (as shown in fig. 1 below) in a plan view, and includes an interface region (referred to as “SL1” by examiner’s annotation shown in fig. 1 below; wherein the interface region SL1 between the region SL and the region PC) formed around the cell edge region (PC) and a core region (a lane region SL functions as a core region) formed around the interface region (SL1) in a plan view.
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With regard to claim 7, Kang discloses the forming of the edge mask pattern (110P1) and the plurality of center mask patterns (110P2) includes: forming a plurality of hard mask layers (110, 120, 130, figs. 3C) on an entire surface of the cell region (CELL REGION) and the peripheral circuit region (PC); and forming the edge mask pattern (110P1) and the plurality of center mask patterns (110P2) only on the cell region (CELL REGION) by patterning the plurality of hard mask layers (110, 120, 130).
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With regard to claim 1, Kang discloses a method (for example, see figs. 1, 3A – 3M) of manufacturing a semiconductor device, the method comprising:
forming an etch target layer (layers 101, 100 function as an etch target layer) within a cell region comprising a cell center region (CELL REGION as shown in figs. 1, 3L) and a cell edge region (referred to as “PC1” by examiner’s annotation shown in fig. 3L below; wherein the region PC1 is formed in the peripheral region PC, as shown in figs. 1, 3L) surrounding the cell center region;
forming an edge mask pattern (referred to as “110P1” by examiner’s annotation shown in fig. 3L below; wherein an edge mask pattern 110P1 is a portion of the hard mark pattern 110P) on an entire surface of the cell edge region (PC1), on the etch target layer (layers 101, 100 function as the etch target layer), and forming a plurality of center mask patterns (referred to as “110P2” by examiner’s annotation shown in fig. 3L below; wherein center mask patterns 110P2 are portions of the hard mark pattern 110P) spaced apart from each other on the cell center region (CELL REGION as shown in fig. 3L) through a quadruple patterning process (four patterning process including, for example, first patterning process as shown in figs. 3A – 3B, a second patterning process as shown in fig. 3F-3G, a third patterning process as shown in fig. 3H-3I, a four patterning process as shown in fig. 3K-3L); and
forming a first etch pattern (referred to as “100P1” by examiner’s annotation shown in fig. 3M below; wherein a first etch pattern 100P1 is a portion of the layer 100) on the cell edge region (PC1), and forming a plurality of second etch patterns (referred to as “100P2” by examiner’s annotation shown in fig. 3M below; wherein the second etch patterns 100P2 are portions of the layer 100P) spaced apart from each other on the cell center region (CELL REGION as shown in fig. 3M) by etching the etch target layer (the etch target portion 100 of the etch target layer 100, 101) using the edge mask pattern (110P1 as shown in fig. 3L below) and the plurality of center mask patterns (110P2 as shown in fig. 3L below) as etch masks,
wherein the first etch pattern (100P1) and the plurality of second etch patterns (100P2) are formed as active patterns (for example, see column 5, lines 42 – 44) respectively in the cell edge region (PC) and the cell center region (CELL REGION).
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Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (9324574) in view of Lee et al. (9281362).
With regard to claim 4, Kang discloses the etch target layer (101, 100) functions as a semiconductor substrate, Kang do not clearly disclose the plurality of second etch patterns are inclined on the semiconductor substrate in a plan view.
However, Lee et al. disclose the plurality of second etch patterns (active regions 134 are etched, functions as second etch patterns) are inclined (as shown in fig. 18H) on the semiconductor substrate (102) in a plan view (a cross-sectional view including a plan view).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Kang’s device to have the plurality of second etch patterns are inclined on the semiconductor substrate in a plan view as taught by Lee et al. in order to secure a high electron mobility efficiency of the active regions for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
5. Claims 8 - 14 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as forming a protection pattern on the plurality of sacrificial patterns of the cell edge region and between the plurality of sacrificial patterns; simultaneously forming a second edge hard mask pattern on the cell edge region and a plurality of second center hard mask patterns spaced apart from each other on the cell center region by etching the second hard mask layer using the protection pattern and the plurality of first spacers as an etch mask; removing the protection pattern from the cell edge region; forming a spacer insulating layer between the plurality of second center hard mask patterns of the cell center region;
simultaneously forming a plurality of second spacers spaced apart from each other
and removing the plurality of second center hard mask patterns between the plurality of second spacers by etching the spacer insulating layer; simultaneously forming an edge mask pattern on the cell edge region and forming a plurality of center mask patterns spaced apart from each other on the cell center region using the plurality of second spacers as an etch mask by etching the first hard mask layer using the second edge hard mask pattern as an etch mask as recited in claim 8.
6. Claims 15 - 20 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as forming a protection pattern filling inner walls and surfaces of the plurality of sacrificial patterns of the cell edge region and between the plurality of sacrificial patterns; simultaneously forming a second edge hard mask pattern on the cell edge region by etching the second hard mask layer and forming a plurality of second center hard mask patterns spaced apart from each other on the cell center region by using the protection pattern and the plurality of first spacers as an etch mask; simultaneously forming a separation pattern between the plurality of sacrificial patterns of the cell edge region and forming a spacer insulating layer between the plurality of second center hard mask patterns of the cell center region; forming a filling layer filling between the plurality of sacrificial patterns and the plurality of second center hard mask patterns on the separation pattern and the spacer insulating layer; removing the separation pattern formed between the plurality of sacrificial patterns of the cell edge region; removing the filling layer of the cell edge region and the cell center region; simultaneously forming a plurality of second spacers spaced apart from each other and removing the plurality of second center hard mask patterns between the plurality of second spacers by etching the spacer insulating layer between the plurality of second center hard mask patterns as recited in claim 15.
Response to Amendment
7. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Response to Arguments
8. Applicant’s arguments filed 08/13/26 have been fully considered but they are not persuasive.
It is argued, at pages of the remarks, that “original claim 1 recites that the claimed cell region comprises a cell center region and a cell edge region. Therefore, the portion of the pattern 100P disposed in the peripheral region of Kang does NOT correspond to the claimed first etch pattern”. However, figs. 1, 3L, 3M of Kang does show a cell region comprising a cell center region (CELL REGION as shown in figs. 1, 3L, 3M) and a cell edge region (a peripheral region PC, as shown in figs. 1, 3L functions as a cell edge region); forming a first etch pattern (referred to as “100P1” by examiner’s annotation shown in fig. 3M below; wherein a first etch pattern 100P1 is a portion of the layer 100) on the cell edge region (the peripheral region PC), and forming a plurality of second etch patterns (referred to as “100P2” by examiner’s annotation shown in fig. 3M below; wherein the second etch patterns 100P2 are portions of the layer 100P) spaced apart from each other on the cell center region (CELL REGION as shown in fig. 3M)
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Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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