DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species A in the reply filed on June 03, 2026 is acknowledged.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Groups II and III, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 03, 2026.
In response to the restriction, upon further consideration and analysis, the original claim 1 is drawn to an apparatus that "comprises a total of five integrated circuit layout tracks on the second semiconductor layer." (Emphasis Examiner) Species A chosen by Applicant in the reply filed June 03, 2026 drawn to Figs 5C and 6 requires six integrated circuit layout tracks. Examiner hereby withdraws the Species restriction but maintains the Inventions restriction and will Examine all claims directed to the invention of Group I.
Claim Objections
Claim 9 is objected to because of the following informalities:
The transition between lines 3 and 4 has the word “and” repeated. Applicant is asked to remove one of the repeated words.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maejima (US 20060250848 A1).
Regarding claim 1, Maejima teaches an apparatus (Fig 4 sense amplifier part, [0068]) comprising: a first sense amplifier (See annotated figure) and a second sense amplifier (See annotated figure); and a second conductor layer (Fig 4 second wiring layer M1, [0069]) comprising two first conductors (See annotated figure), two second conductors (See annotated figure) substantially parallel to the two first conductors (See annotated figure), and a landing pad (See annotated figure), wherein: the first conductors (See annotated figure) each comprise one integrated circuit layout track (See annotated figure; shaded area) on the second conductor layer (Fig 4 second wiring layer M1, [0069]); the second conductors (See annotated figure) each comprise one integrated circuit layout track (See annotated figure; shaded area) on the second conductor layer (Fig 4 second wiring layer M1, [0069]); the landing pad (See annotated figure) comprises two integrated circuit layout tracks (See annotated figure; shaded area) on the second conductor layer (Fig 4 second wiring layer M1, [0069]); and the apparatus (Fig 4 sense amplifier part, [0068]) comprises a total of five integrated circuit layout tracks (See annotated figure; shaded areas) on the second conductor layer (Fig 4 second wiring layer M1, [0069]).
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Regarding claim 2, Maejima teaches an active area (Fig 4 active region AA, [0069]) disposed in a substrate (Fig 4 not shown; Examiner notes that a substrate would be an inherent feature as the layout would have to be made on something MPEP 2112), the second conductor layer (Fig 4 second wiring layer M1, [0069]) disposed above (Fig 4) the active area (Fig 4 active region AA, [0069]).
Regarding claim 3, Maejima teaches a first conductor layer (Fig 4 layer comprising active region AA) comprising an active area (Fig 4 active region AA, [0069]) comprising the first sense amplifier and the second sense amplifier.
Regarding the sense amplifier, Examiner notes the structure of Maejima is substantially the same as shown in Fig 7B of the instant application. Further, [00207]-[00208] of the instant application discloses the active area portions 706a1 and 706b1 include transistors that are used to form a first and second sense amplifier. In addition, Maejima teaches that Fig 4 is a sense amplifier part ([0068]) implying there are sense amplifiers located in the part. MPEP 2112.01
Regarding claim 4, Maejima teaches a first conductor layer (Fig 4 layer comprising active region AA) comprising a first active area (Fig 4 active region AA, [0069]) portion comprising the first sense amplifier and a second active area (Fig 4 active region AA, [0069]) portion comprising the second sense amplifier.
Regarding the sense amplifier, Examiner notes the structure of Maejima is substantially the same as shown in Fig 7B of the instant application. Further, [00207]-[00208] of the instant application discloses the active area portions 706a1 and 706b1 include transistors that are used to form a first and second sense amplifier. In addition, Maejima teaches that Fig 4 is a sense amplifier part ([0068]) implying there are sense amplifiers located in the part. MPEP 2112.01
Regarding claim 5, Maejima teaches a first conductor layer (Fig 4 first wiring layer M0, [0069]) comprising a first active area portion (Fig 4 portion of first wiring layer on top left active region AA), a second active area portion (Fig 4 portion of first wiring layer on bottom left active region AA) and a third active area portion (Fig 4 portion of first wiring layer the connects the top left and bottom left wiring area portions) that couples the first active area portion (Fig 4 portion of first wiring layer on top left active region AA) and the second active area portion (Fig 4 portion of first wiring layer on bottom left active region AA).
Regarding claim 6, Maejima teaches a third conductor layer (Fig 4 gate wiring GC, [0069]) comprising two third conductors (See annotated figure) substantially perpendicular to (Fig 4) the two first conductors (See annotated figure).
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Regarding claim 7, Maejima teaches a third conductor layer (Fig 4 gate wiring GC, [0069]) comprising two third conductors (See annotated figure of claim 6) each coupled to (the third conductors are electrically coupled to the first conductors) a corresponding one of the first conductors (See annotated figure).
Regarding claim 8, Maejima teaches the first conductors (See annotated figure of claim 1) comprise bit lines (Fig 4 bitlines BL_even and BL_odd, [0037]) of a three dimensional non-volatile memory array (Fig 1 NAND cell units of cell array, [0039]; memory cells are three dimensional).
Regarding claim 9, Maejima teaches the two first conductors (See annotated figure of claim 1) comprise: a first first conductor (Fig 4 leftmost bitline BL_even, [0037]) coupled to a first bit line switch (Fig 3 left transistor in 10 cell source driver) disposed in a first bit line hookup region (Fig 3 left region in 10 cell source driver); and and a second first conductor (Fig 4 leftmost bitline BL_odd, [0037]) coupled to a second bit line switch (Fig 3 right transistor in 10 cell source driver) disposed in a second bit line hookup region different from the first bit line hookup region (Fig 3 right transistor in 10 cell source driver).
Regarding claim 10, Maejima teaches the two first conductors (See annotated figure of claim 1) are disposed parallel to a first axis (Fig 4 left-right direction), and comprise: a first first conductor (Fig 4 leftmost bitline BL_even, [0037]) coupled to a first bit line hookup region (Figs 3 and 4 left region of 10 cell source driver) disposed in a first direction (Fig 4 left) along the first axis (Fig 4 left-right direction); and and a second first conductor coupled to a second bit line hookup region (Figs 3 and 4 right region of 10 cell source driver) disposed in a second direction (Fig 4 right) along the first axis (Fig 4 left-right direction), wherein the first direction (Fig 4 left) is opposite the second direction (Fig 4 right).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hisada et. al. (US 20110176347 A1) teaches multiple sense amplifier layout configurations.
Morozumi et. al. (US 20200335513 A1) teaches a planar view with five circuit layout tracks on a same layer
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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