Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 7, 15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 20150357413).
Regarding claim 1. Fig 1A (a cross-sectional view) and Fig 1B (top plan view) of Zhang discloses A semiconductor device, comprising:
a plate layer 102;
gate electrodes 3 [0021] that are on the plate layer, extend in a first direction (Y, vertical) that is perpendicular to an upper surface of the plate layer, and are spaced apart from each other (due to 19b which is interposed between 3a and 3b);
interlayer insulating layers 19 [0021] that are alternately stacked with the gate electrodes on the plate layer (Fig 1A); and
a channel structure 1/2 that extends into the gate electrodes and in the first direction (Fig 1A), wherein the channel structure comprises a channel filling layer 2 that extends in the first direction, a channel layer 1 [0014] that at least partially surrounds the channel filling layer (Fig 1B),
charge storage layers 9 [0022] that are between the gate electrodes and the channel layer and spaced apart from each other in the first direction (Fig 1A, Fig 1B),
a first dielectric layer 7 [0022] between the gate electrodes and the charge storage layers (Fig 1A, Fig 1B), and
a second dielectric layer 11 between the channel layer and the charge storage layers (Fig 1A, Fig 1B),
wherein the channel layer includes first convex portions (the inwardly protruding dome-shaped portions of channel layer 1 facing channel fill layer 2 define convex portions. The apexes of these convex portions are located at levels corresponding to interlevel insulating layer 19b positioned between adjacent gate electrodes 3a and 3b, as shown in Fig. 1A.) that extend toward the channel filling layer from a side surface of the channel layer that contacts the channel filling layer (Fig 1A), and
wherein vertices (the apexes of these convex portions are located at levels corresponding to interlevel insulating layer 19b positioned between adjacent gate electrodes 3a and 3b, as shown in Fig. 1A) of the first convex portions are at first levels in the first direction that are between each level of a pair of adjacent gate electrodes in the first direction (Fig 1A).
Regarding claim 2. Zhang discloses The semiconductor device of claim 1, wherein the vertices of the first convex portions are adjacent to an upper end of each of the interlayer insulating layers and a lower end of each of the interlayer insulating layers (Fig 1A).
Regarding claim 4. Zhang discloses The semiconductor device of claim 1, wherein the second dielectric layer comprises second convex portions that extend from a side surface of the second dielectric layer toward the channel filling layer (Fig 1A: because of same profile of 1), wherein the side surface of the second dielectric layer contacts the channel layer (Fig 1A).
Regarding claim 7. Zhang discloses The semiconductor device of claim 1, wherein the first dielectric layer comprises a single layer that extends in the first direction, and the second dielectric layer comprises a single layer that extends in the first direction (Fig 1A, 1B: single continuous layer from top to bottom).
Regarding claim 15. Fig 1A (a cross-sectional view) and Fig 1B (top plan view) of Zhang discloses A semiconductor device, comprising:
a plate layer 102a;
gate electrodes 3 that are on the plate layer, extend in a first direction (Y, vertical) that is perpendicular to an upper surface of the plate layer, and are spaced apart from each other;
interlayer insulating layers 19 that are alternately stacked with the gate electrodes on the plate layer (Fig 1A); and
a channel structure 1/2 that extends into the gate electrodes and in the first direction, wherein the channel structure comprises a channel filling layer 2, a channel layer 1on the channel filling layer, a second dielectric layer 11 on the channel layer, charge storage layers 9 on the second dielectric layer, and first dielectric layers 7 on the charge storage layers, and
wherein the channel filling layer comprises inwardly curved portions that extend toward an inside of the channel filling layer (Fig 1A), and
wherein a first level (the level of 19a from top) of a first curved portion of the curved portions is at a level equal to or adjacent to an upper end of a first interlayer insulating layer of the interlayer insulating layers, and
wherein a second level (the level of 19b from top) of a second curved portion of the curved portions is at a level equal to or adjacent to a lower end of the first interlayer insulating layer the interlayer insulating layers.
Regarding claim 18. Zhang discloses The semiconductor device of claim 15,
wherein the channel layer includes convex portions that extend toward the channel filling layer from a side surface of the channel layer that contacts the channel filling layer (Fig 1A), and
wherein vertices of the convex portions are at second levels between the upper end and the lower end of each of the interlayer insulating layers (Fig 1A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6, 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20150357413) in view of Son (US 20210074720; in the IDS 2/26/24).
Regarding claim 5. Zhang discloses The semiconductor device of claim 4, wherein the first dielectric layer comprises third convex portions that extend from a side surface of the first dielectric layer toward the second dielectric layer (Fig 1A: because of same profile of 1).
But Zhang does not expressly disclose wherein the side surface of the first dielectric layer contacts the second dielectric layer.
However, Fig 9 of Son discloses the side surface of the first dielectric layer 38 contacts the second dielectric layer 42 (in the area of 22).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhang's dielectric stack to provide direct contact between portions of first dielectric layer 7 and second dielectric layer 11 in regions where the charge storage layer is absent, as taught by Son, because Son teaches that continuous dielectric layers surrounding discrete charge storage regions provide improved electrical insulation and charge confinement while maintaining structural integrity of the memory stack. Such modification merely applies a known dielectric arrangement to Zhang's substantially similar charge-trap memory structure to obtain the predictable benefit of improved charge isolation.
Regarding claim 6. Zhang discloses The semiconductor device of claim 1,
wherein each of the charge storage layers 9 includes a first side surface that contacts the first dielectric layer and a second side surface that contacts the second dielectric layer (Fig 1A).
But Zhang does not expressly disclose wherein a length of the first side surface is less than a length of the second side surface.
However, Fig 9 of Son discloses a length (40p3: vertical length) of the first side surface is less than a length (40p2: vertical length) of the second side surface [0058].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure Zhang's charge storage layer such that the first side surface is shorter than the second side surface, as taught by Son, because Son teaches that a reduced storage-layer dimension in selected regions permits formation of isolated charge-storage regions while maintaining continuous dielectric layers. Incorporating Son's dimensional relationship into Zhang would have predictably improved electrical separation between adjacent charge-storage regions and reduced charge migration.
Regarding claim 14. Zhang discloses The semiconductor device of claim 1. But Zhang does not expressly disclose further comprising:
a first horizontal conductive layer and a second horizontal conductive layer, wherein the second horizontal conductive layer is between the plate layer and the gate electrodes, and
wherein the first horizontal conductive layer defines a recess portion that extends in the first direction and that contacts the channel layer.
However, Fig 2 of Son discloses a first horizontal conductive layer 59 and a second horizontal conductive layer 17, wherein the second horizontal conductive layer is between the plate layer 3 and the gate electrodes 65 (Fig 2), and
wherein the first horizontal conductive layer defines a recess portion that extends in the first direction and that contacts the channel layer 44 (Fig 4).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Son's first and second horizontal conductive layers into Zhang's semiconductor memory structure because Son teaches that such conductive layers provide electrical connection and biasing of the vertical memory string while maintaining compact vertical integration. Incorporating the conductive-layer arrangement of Son into Zhang would have been a predictable use of a known NAND architecture feature to provide improved electrical routing and device integration.
Regarding claim 17. Zhang discloses The semiconductor device of claim 15, Zhang discloses wherein the first dielectric layers comprise a single layer between a pair of adjacent gate electrodes of the gate electrodes (Fig 1A: single continuous layer from top to bottom), and
wherein the second dielectric layer comprises a single layer between the pair of adjacent gate electrodes (Fig 1A: single continuous layer from top to bottom).
But Zhang does not expressly disclose wherein the charge storage layers comprises a plurality of layers that are spaced apart from each other between the pair of adjacent gate electrodes.
Fig 4A of Son discloses the charge storage layers 40 comprises a plurality of layers 40that are spaced apart from each other between the pair of adjacent gate electrodes 65 [0049].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Son's plurality of spaced-apart charge storage layers into Zhang's memory structure in order to provide enhanced electrical isolation between adjacent storage regions, thereby mitigating charge interference and reducing the likelihood of data corruption between adjacent memory cells. Such modification represents the predictable use of a known charge-storage arrangement to improve memory reliability.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 20220045082) in view of Zhang (US 20150357413).
Regarding claim 19. Jeong discloses A data storage system [0123], comprising:
a semiconductor storage device 1100 comprising a first semiconductor structure 1100F (also ‘PERI’ in Fig 2A), a second semiconductor structure 1100S (also ‘CELL’ in Fig 2A) on the first semiconductor structure (Fig 12), and an input/output pad 1101 electrically connected to the first semiconductor structure; and
a controller 1220 connected to the semiconductor storage device through the input/output pad (Fig 11),
wherein the second semiconductor structure includes:
a plate layer 102 [0031];
gate electrodes 130 that are on the plate layer, extend in a first direction (vertical) that is perpendicular to an upper surface of the plate layer, and are spaced apart from each other (Fig 2A, [0031]);
interlayer insulating layers 120 that are alternately stacked with the gate electrodes on the plate layer (Fig 2A, [0031]); and
a channel structure (Fig 2A, CH) that extends into the gate electrodes and in the first direction, wherein the channel structure comprises a channel filling layer 150, a channel layer 140 on the channel filling layer, a second dielectric layer [0056] on the channel layer, charge storage layers [0056] on the second dielectric layer, and first dielectric layers [0056] on the charge storage layers (Fig 2A, [0056]: Although not specifically illustrated, Jeong discloses the claimed stack of structures).
But Jeong does not expressly disclose wherein the channel layer includes convex portions that extend toward the channel filling layer from a side surface of the channel layer, and
wherein vertices of the convex portions are at first levels in the first direction that are levels between each level of a pair of adjacent gate electrodes in the first direction.
However, Zhang discloses the channel layer includes convex portions that extend toward the channel filling layer from a side surface of the channel layer (the inwardly protruding dome-shaped portions of channel layer 1 facing channel fill layer 2 define convex portions. The apexes of these convex portions are located at levels corresponding to interlevel insulating layer 19b positioned between adjacent gate electrodes 3a and 3b, as shown in Fig. 1A.), and
wherein vertices of the convex portions are at first levels in the first direction that are levels between each level of a pair of adjacent gate electrodes 3 in the first direction.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the channel structure of Jeong to include the convex channel-layer profile taught by Zhang, wherein the convex portions extend toward the channel filling layer and have vertices positioned between adjacent gate electrodes, because Zhang teaches that such a shaped channel profile may be formed in a vertical charge-trap memory structure and provides a non-uniform channel geometry corresponding to regions between adjacent gate electrodes and interlayer insulating layers. Incorporating Zhang's channel profile into Jeong's substantially similar vertical memory-cell architecture would have represented the predictable use of a known channel-structure configuration in an analogous semiconductor memory device to obtain the known benefits associated with controlled channel geometry, including electric-field distribution control, charge-storage optimization, and memory-device reliability improvement.
Regarding claim 20. Jeong in view of Zhang discloses The data storage system of claim 19, wherein the vertices of the convex portions are in regions that oppose the interlayer insulating layers on the side surface of the channel layer (Zhang further discloses that the apexes (vertices) of the inwardly protruding dome-shaped convex portions of channel layer 1 are located in regions corresponding to interlevel insulating layer 19b disposed between adjacent gate electrodes 3a and 3b, as shown in Fig. 1A).
Allowable Subject Matter
Claims 3, 8-13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the channel layer has a minimum width of the plurality of widths between the vertices of the first convex portions”.
Regarding claim 8. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “first insulating layers between the interlayer insulating layers and the first dielectric layer; and second insulating layers, wherein each second insulating layer of the second insulating layers comprises upper surfaces, lower surfaces, and first side surfaces that contact a respective first insulating layer of the first insulating layers”.
Regarding claim 13. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a length of a given charge storage layer of the charge storage layers in the first direction may be greater than or equal to a value obtained by subtracting a sum of twice a length of the first dielectric layer from a sum of a length of a respective gate electrode of the gate electrodes and twice a thickness of a respective gate dielectric layer of the gate dielectric layers”.
Regarding claim 16. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the channel layer comprises two points that define a minimum width of the plurality of widths, and wherein the two points are in a region that opposes each of the interlayer insulating layers”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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