DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-10) and Species A (Fig. 5; claims 1-4 and 6-10) in the reply filed on 9 June 2026 is acknowledged. Claims 5 and 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. The election requirement is deemed proper and made final. Applicants are reminded to indicate the withdrawn status of claim 5 in their next submission of a claim listing.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 22, recites “the second semiconductor region,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with the remainder of the claim, the claim will be interpreted as “the second semiconductor regions.” Claims 2-4 and 6-10 are rejected due their dependency from base claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 6-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito et al. (US20220285553A1).
Regarding claim 1, as interpreted in view of the indefiniteness rejection, Ito teaches in Figs. 2 and 3 a semiconductor device, comprising:
a first electrode (11) {[0024]};
a first semiconductor region (1 and/or 5) of a first type (n-type) above the first electrode (11), the first semiconductor region (1 and/or 5) including first and second regions (1st and 2nd regions) {see, e.g., Annotated Copy of Ito’s Fig. 2, below; [0024]};
a plurality of second semiconductor regions (2) of a second type (p-type) on the first region (1st region) {[0024]};
a plurality of third semiconductor regions (3) of the first type (n-type) on the second semiconductor regions (2) {[0024]};
a second electrode (12) above the third semiconductor regions (3) and electrically connected to the third semiconductor regions (3) {[0031]};
a plurality of first structures (13, 21) in the first region (1st region) and surrounded by the second and third semiconductor regions (2, 3), each of the first structures (13, 21) including a first insulating region (21) and a first conductive region (13) inside the first insulating region (21), the first structures (13, 21) being arranged in a second direction (D2) perpendicular to a first direction (D1) from the first electrode (11) toward the second electrode (12) and in a third direction perpendicular (D3) to the first and second directions (D1, D2) {[0024]};
a plurality of second structures (13, 21) in the second region (2nd region), each of the second structures (13, 21) including a second insulating region (21) and a second conductive region (13) inside the second insulating region (21), the second structures (13, 21) being arranged in the second and third directions (D2, D3) {[0024]};
a third electrode (10 or 10, 15a) surrounding the first and second structures (13, 21) and extending along the second and third directions (D2, D3) {[0024, 0033]};
a first insulating portion (10a) between the second semiconductor regions (2) and the third electrode (10) {[0024, 0028]};
a second insulating portion (22 and/or 31) above the second region (2nd region) {[0024]}; and
a wiring portion (15 and/or 15a) above the second insulating portion (22 and/or 31) and electrically connected to the third electrode (10 or 10, 15a) {[0024, 0033]}.
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Regarding claim 2, Ito teaches the semiconductor device according to claim 1, and Ito further teaches wherein
the second region (2nd region) includes a first portion (1st portion including 13, 21 and below 31) including the second structures (13, 21) and a second portion (2nd portion around 13, 21 and below 31) around the first portion (1st portion including 13, 21) {Fig. 3},
the wiring portion (15 and/or 15a) includes a first wiring region (region of 15 and/or 15a above 13, 21) above the first portion (1st portion including 13, 21 and below 31) and a second wiring region (region of 15 and/or 15a above region outside perimeter of 13, 21) above the second portion (2nd portion around 13, 21 and below 31) {Figs. 2, 3}, and
a width of the first wiring region (region of 15 and/or 15a above 13, 21) is equal to a width of the third electrode (10 or 10, 15a) { Figs. 2, 3; “a width” may be any width and not necessarily the diameter}.
Regarding claim 3, Ito teaches the semiconductor device according to claim 2, and Ito further teaches wherein a width of the second wiring region (region of 15 and/or 15a above region outside perimeter of 13, 21) is equal to the width of the third electrode (10 or 10, 15a) {Figs. 2, 3; “a width” may be any width and not necessarily the diameter}.
Regarding claim 6, Ito teaches the semiconductor device according to claim 1, and Ito further teaches further comprising: a third insulating portion (31) between the wiring portion (15 and/or 15a) and the second insulating portion (22) {Fig. 3; [0024]}.
Regarding claim 7, Ito teaches the semiconductor device according to claim 1, and Ito further teaches wherein the first region (1st region) is located at a position corresponding to a center of the first electrode (11) in the second and third directions (D2, D3), and the second region (2nd region) surrounds the first region (1st region) {see, e.g., Annotated Copy of Ito’s Fig. 2, below}.
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Regarding claim 8, Ito teaches the semiconductor device according to claim 1, and Ito further teaches wherein the first structures (13, 21) are surrounded by the second and third semiconductor regions (2, 3) on the first region (1st region) {Figs. 2, 3}.
Regarding claim 9, Ito teaches the semiconductor device according to claim 1, and Ito further teaches further comprising:
a plurality of first connection portions (12a) that connect the second electrode (12) and the second and third semiconductor regions (2, 3) {Fig. 3; [0031]}; and
a plurality of second connection portions (16, 16a, 16b) each connects the second electrode (12) and a corresponding one of the first conductive regions (13) of the first structures (13, 21) {Fig. 3; [0034]}.
Regarding claim 10, Ito teaches the semiconductor device according to claim 1, and Ito further teaches further comprising: a reduced surface field region (3) on the second region (2nd region) and surrounding one or more of the second structures (13, 21) {the citation of Ito’s reference character “3” in base claim 1 was limited to features within the recited “first region,” whereas Ito’s reference character “3” used solely in claim 10 is limited to a feature within the recited “second region}.
Examiner’s Note: A reduced surface field region may be differently doped with respect to another (e.g., a drift region) for the purpose of lowering an electric field at a semiconductor surface. Ito’s region 3 is n+ doped and the underlying drift region is n doped. See, e.g., Pendharkar (US20110180870A1) – Abstract, RESURF region is the same conductivity type as the drift region and is more heavily doped than the drift region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ito as applied to claim 1 above, and further in view of Yasutake et al. (US20230261105A1).
Regarding claim 4, Ito teaches the semiconductor device according to claim 1, but Ito does not teach wherein an upper surface of the third electrode is aligned with an upper surface of the wiring portion in the first direction.
In an analogous art, Yasutake teaches in Fig. 6 and paragraph [0039] an upper surface of a third electrode (30) is aligned with an upper surface of a wiring portion (40) in a first direction (Z). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ito’s semiconductor device based on the teachings of Yasutake, to achieve the above-identified subject matter, for depositing the wiring portion and the third electrode in the same layer for reducing manufacturing resources (e.g., operations, materials, time, etc.). Moreover, all the claimed elements (e.g., surface, electrode, wiring) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yasutake) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Katoh et al. (US20190123197A1) teaches a semiconductor device includes a first conductivity type first semiconductor region, a second semiconductor region on the first semiconductor region, a third semiconductor region on the second semiconductor region, a first insulating portion extending inwardly of, and surrounded by, the first semiconductor region, a gate electrode extending inwardly of the first insulating portion and spaced from the second semiconductor region in a second direction that intersects a first direction extending from the first semiconductor region to the second semiconductor region, by the first insulating portion, and a first electrode including a portion spaced from the first semiconductor region in the second direction by the first insulating portion, and surrounded by the first insulating portion and the gate electrode.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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