DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 14A and 214B in Figures 2A-2C, STI 740 in Figures 7A-7C, and 1150 in Figure 11A-11C. These labels should be added to the drawings. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because in Fig 20, step 2020 “For the gate contact” should be “Form the gate contact”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In Paragraph [0007], line 1, “In seem embodiments” should be “In some embodiments”
In Paragraph [0019], line 1, “partially etched” should be “partially etching”
In Paragraph [0030], line 1, “after formation the” should be “after forming the”
In Paragraph [0031], line 2, “contact dielectric cap contact” should be “contact dielectric cap”
In Paragraph [0034], line 1, “formation of additional” should be “formation of an additional”
In Paragraphs [0035], [00115], and [00116], line 1, “after the patterning the” should be “after patterning the” or “after the patterning of the”
In Paragraph [00124], line 4, “by filling by a” should be “by filling a”
Appropriate correction is required.
Claim Objections
Claims 12, 18, & 20 are objected to because of the following informalities:
In Claim 12, line 4, “first second dielectric layer” should be “the first dielectric layer”
In Claim 17, line 1, “partially etched” should be “partially etching”
In Claim 20, line 5, “second gate channels” should be “second gate channel”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Peng et al. (US 20230253325 A1).
Regarding Claim 1, Peng et al. teaches a Semiconductor device comprising:
A gate contact over a first gate channel of two adjacent gate channels; (In Fig 28B 114 is in contact of with at least one of the gate regions, of which a gate region comprises 130 and 104) and a first dielectric layer encapsulating a lower portion of a second dielectric layer and covering a first side of the second dielectric layer (Figure 28B shows two dielectric layers 164 & 162, with the first dielectric layer, 164, encapsulating the sides including the lower half of the second dielectric layer, 162), wherein:
The first dielectric layer is extended vertically between the two adjacent gate channels (Fig 28B shows the two dielectric layers, 162 and 164, vertically between the gate channels, 130 and 104)
The gate contact is connected to an upper portion of the first side of the second dielectric layer (Fig 28B shows 114 covering and contacting the upper portion of 162).
Regarding Claim 2, Peng et al. teaches the first dielectric layer connected to the two adjacent gate channels (Fig 28B shows that the first dielectric layer, 164, is connected to the two adjacent gates, 130 and 104, through the second dielectric layer, 162, which is in direct contact with the gate channels)
Regarding Claim 3, Peng et al. teaches the gate contact further covering portions of a top surface of the second dielectric layer (Fig 28B shows 114 on top of the 162)
Regarding Claim 4, Peng et al. teaches the semiconductor further comprising:
A first self-aligned contact (SAC) dielectric cap over the first gate channel of the two adjacent gate channels (Fig 28B shows multiple dielectric layers, 120b and 112, which both serve to cap a gate channel, 130 and 104); and
A second SAC dielectric cap over a second gate channel of the two adjacent gate channels (Fig 28B shows a second set of dielectric layers, 120a and 112, which both serve to cap the second gate channel, 130 and 104);
Wherein the gate contact is connected to the first SAC dielectric cap (28B shows that the gate contact, 114, is in between and directly touching the two SAC dielectric caps).
Regarding Claim 6, Peng et al. teaches a backside power delivery network (BSPDN) on a backside of the semiconductor device (Paragraph 0155 describes a backside power rail on the backside of the semiconductor device).
Regarding Claim 7, Peng et al. teaches the gate contact partially etched into the first SAC dielectric cap and the second dielectric layer (see figure 23C, gate contact 114 is in contact with SAC dielectric cap 112 and 120b, and second dielectric layer 162, there is broadly 'etched into' - noting etching is a method step and inside a structure claim is interpreted as the resulting product of the process - see also MPEP 2113 I for product by process claim interpretation).
Regarding Claim 10, Peng et al. teaches that the first SAC dielectric cap and the second SAC dielectric cap are made of silicon nitride (Paragraph 0021 states that 120b is able to be made out of silicon nitride. Paragraph 0022 states that 112 is able to be made out of silicon nitride)
Regarding Claim 11, Peng et al. teaches the first dielectric layer being made of silicon dioxide and the second dielectric layer being made of silicon nitride (Paragraph 0031 states that the first dielectric layer, 164, is able to be silicon dioxide and that the second dielectric layer, 162, is able to be silicon nitride)
Regarding Claim 12, Peng et al. teaches a method for fabrication of a semiconductor device, the method comprising:
Forming a gate contact over a first gate channel of two adjacent gate channels; (In Fig 28B 114 is in contact of with at least one of the gate regions, of which a gate region comprises 130 and 104);
encapsulating a lower portion of a second dielectric layer by a first dielectric layer (Figure 28B shows two dielectric layers 164 & 162, with the first dielectric layer, 164, encapsulating the lower sides of the second dielectric layer, 162);
covering a first side of the second dielectric layer by first second dielectric layer (Interpreting this to mean that the first side of the second dielectric layer is covered by the first dielectric layer. Figure 28B the first dielectric layer, 164, encapsulating the sides of the second dielectric layer, 162) and
Connecting the gate contact to an upper portion of the first side of the second dielectric layer (Fig 28B shows 114 covering the upper portion of 162).
Wherein the first dielectric layer is extended vertically between the two adjacent gate channels (Fig 28B shows the two dielectric layers, 162 and 164, vertically between the gate channels, 130 and 104)
Regarding Claim 13, Peng et al. teaches the first dielectric layer connected to the two adjacent gate channels (Fig 28B shows that the first dielectric layer is connected to the two adjacent gates, 130 and 104, through the second dielectric layer, 162, which is in direct contact with the gate channels)
Regarding Claim 14, Peng et al. teaches covering portions of a top surface of the second dielectric layer by the gate contact (Fig 28B shows 114 on top of the 162)
Regarding Claim 15, Peng et al. teaches the method further comprising:
forming first self-aligned contact (SAC) dielectric cap over the first gate channel of the two adjacent gate channels (Fig 28B shows multiple dielectric layers, 102b and 112, which both serve to cap a gate channel, 130 and 104); and
forming a second SAC dielectric cap over a second gate channel of the two adjacent gate channels (Fig 28B shows a second set of dielectric layers, 102b and 112, which both serve to cap the second gate channel, 130 and 104); and
connecting the gate contact to the first SAC dielectric cap (28B shows that the gate contact, 114, is in between the two SAC dielectric caps).
Regarding Claim 16, Peng et al. teaches forming a backside power delivery network (BSPDN) on a backside of the semiconductor device (Paragraph 0155 describes a backside power rail on the backside of the semiconductor device).
Regarding Claim 18, Peng et al. teaches the method further comprising:
Forming a metal track (M1 track) over the gate contact (Fig 29B shows a metal line, 210, above the gate contact, 114); and
Forming a via connecting the first gate channel to the M1 track via the gate contact (Fig 29B shows a via, 115, which is between the gate channel, 130 and 104, and the metal track, 210, with the via being in contact with the gate contact, 114).
Regarding Claim 20 Peng et al. teaches a Semiconductor device comprising:
A dielectric structure between a first gate channel and a second gate channel (Fig 28B shows the two dielectric layers which make up the dielectric structure, 162 and 164, between the gate channels, 130 and 104)
A gate contact over the first gate channel (In Fig 28B 114 is in contact of with at least one of the gate regions, of which a gate region comprises 130 and 104) and covering an upper portion of the dielectric structure (Fig 28B shows 114 on top of the 162); and
A first self-aligned contact (SAC) dielectric cap and a second SAC dielectric cap over the first gate channel and the second gate channels, respectively (Fig 28B shows two sets of dielectric layers, 102b and 112, which both serve to cap the first and second gate channels, which the gate channel comprises of 130 and 104).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9, & 19 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 20230253325 A1) in view of Jain et al. (US 2023/0268389 A1).
Regarding Claim 8, Peng et al. teaches the method further comprising:
a metal track (M1 track) over the gate contact (Fig 29B shows a metal line, 210, above the gate contact, 114.); and
a via connecting the first gate channel to the M1 track via the gate contact (Fig 29B shows a via, 115, which is between the gate channel, 130 and 104, and the metal track, 210, with the via being in contact with the gate contact, 114).
Peng et al. does not explicitly teach the M1 track being a signal track.
Jain et al. teaches the metal line being a signal line (004 describes the M1 lines as being signal lines).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng et al. to make the metal track a signal track as taught by Jain et al. because it allows for electrons to quickly travel between resistors with low electrical resistance, which improves the efficiency of the semiconductor, allowing the device to operate with higher power.
Regarding Claim 9, Peng et al. does not teach the gate contact being located at a negative field-effect transistor (NFET) to NFET cell boundary, or at a positive FET (PFET) to PFET cell boundary.
Jain et al. teaches the gate contact being located at a negative field-effect transistor (NFET) to NFET cell boundary, or at a positive FET (PFET) to PFET cell boundary (Paragraph 0053 teaches a gate-all around (GAA) FET that surrounds the channel region on all sides. This boundary is a NFET or a PFET. As the gate contact from Peng et al. is connected to the gate contact would be located in this cell boundary).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng et al. to locate the gate contact in a NFET or PFET cell boundary as taught by Jain et al. as it increases the contact between the gate contact and the channel, providing better electrical control over the channel (Paragraph 0053 of Jain et al.).
Regarding Claim 19, Peng et al. does not teach forming the gate contact at a negative field-effect transistor (NFET) to NFET cell boundary, or at a positive FET (PFET) to PFET cell boundary.
Jain et al. teaches forming the gate contact at a negative field-effect transistor (NFET) to NFET cell boundary, or at a positive FET (PFET) to PFET cell boundary (Paragraph 0053 teaches a gate-all around (GAA) FET that surrounds the channel region on all sides. This boundary is a NFET or a PFET. As the gate contact from Peng et al. is connected to the gate contact would be located in this cell boundary).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng et al. to form the gate contact at a NFET or PFET cell boundary as taught by Jain et al. as it increases the contact between the gate contact and the channel, providing better electrical control over the channel (Paragraph 0053 of Jain et al.).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 20230253325 A1) in view of Grant et al. (US 20230163020 A1)
Regarding Claim 17, Peng et al. does not teach partially etching the gate contact into the first SAC dielectric cap and the second dielectric layer.
Grant et al. teaches partially etching the gate contact into the first SAC dielectric cap and the second dielectric layer (Paragraph 0063 describes a gate contact being etching into an interlayer dielectric connected to the gate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Peng et al. by partially etching the gate contact as taught by Grant et al. in order to allow for precise integration with the gate channel with the surrounding dielectric layers while preserving the insulating properties of the dielectric layers, which helps ensure long term device performance.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art does not teach or render obvious wherein a top surface of portions of the first dielectric layer, a top surface of the second dielectric layer, a top surface of the first SAC dielectric cap, and a top surface of the second SAC dielectric cap are coplanar and, in the combination, as claimed.
As the two dielectric layers are not coplanar in this configuration of Peng et al.’s device, with the second dielectric layer covering the top surface of the first dielectric layer, it would not be obvious to one of ordinary skill in the art to teach in two dielectric layers that are level with the SAC dielectric cap.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Xie et al. (US 20240332293 A1) shares the same structure, having the two dielectric layers vertically in between two adjacent gate channels. On top of one of the gate channels is a gate contact within a nFET or pFET boundary that also covers the top of the second dielectric layer along with two dielectric layers that cap the two channel regions. It then has a BSPDN and a via that connect the gate channel to the metal (signal) tracks through the gate contact.
Dai et al. (US 20210375751 A1) shares a similar structure wherein it contains a first dielectric layer covering a second vertically between two layers, with a contact layer covering the top of one and partially covering the edge of the adjacent layer.
Cheng et al. (US 20200083106 A1) has a dielectric layer in between two gate channels that has a contact covering the top edges of the channel and the dielectric layer.
Su et al. (US 11621197 B2) shares a similar structure in which two vertical dielectric layers are in between adjacent gate channels with a dielectric cap and a contact above at least one of the channels.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLOTTE ELIZABETH HARBOTTLE whose telephone number is (571)270-0644. The examiner can normally be reached Monday-Friday 7:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.E.H./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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