Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1-20 are currently pending and have been considered below. Claims 1 and 11 are independent claims.
Response to Arguments
Applicant’s arguments with respect to claim 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 9-13 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang(US Publication No. 20180278418 A1) in view of Duncan(US Patent No. 9425803 B1 ) in further view of Jang(US Publication No. 20060073653A1)
Regarding Claim 1:
Chang discloses:
A physical unclonable function (PUF) code generating apparatus, comprising: a PUF code generating element, configured to generate a PUF code(Chang, [0014], A circuit that generates a PUF is, or includes, a physical entity embodied in a physical structure which produces a code that is easy to evaluate but hard to predict.);
and a PUF code storage element, coupled to the PUF code generating element, and configured to receive and store the PUF code and comprise:(Chang, [0094], A command or set of commands can include a first command (1) which causes transfer (2) of a PUF key from a PUF circuit 3337 to key store 3335. The command or set of commands can identify and address the memory array 3311 to provide the location in a memory array of the key store 3335 or otherwise identify the PUF key store. In some embodiments, the PUF key is modified by glue logic, such as a hash function or other function controlled by the security logic which has complementary logic in the host, before storage in the key store),
Chang does not disclose:
configured to have a characteristic of bit data that randomly changes,
Duncan discloses:
configured to have a characteristic of bit data that randomly changes,(Duncan, Col. 1-2, lines 65-67 and 1-2, the bits in a first state with charge on selected bit capacitors; stopping bit refresh for a first predetermined time; re-enabling refresh for a second predetermined time to read and refresh charge on all bits; Col. 5, lines 55-59, the bit cell can be shown as reading a ‘1’ when charge is stored on the capacitor and reading a ‘0’ when the charge as been removed. Once the bit cell capacitor has been charged, it will slowly lose charge through leakage through the capacitor and transistor.)
Chang in view of Duncan do not disclose:
and comprise: flash memory cells, and each of the flash memory cells comprising: a floating gate layer
a semiconductor
and a tunnel oxide layer located between the floating gate layer and the semiconductor layer,
wherein in the tunnel oxide layer, a ratio of a minimum thickness of a peripheral area to a maximum thickness of a central area is less than 0.99
Jang discloses:
and comprise: flash memory cells, and each of the flash memory cells comprising: a floating gate layer (Jang, [0005], a flash memory cell of a flash memory device has a structure that includes a floating gate, an interlayer dielectric layer, and a control gate on a semiconductor substrate. [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) [0013], a first polysilicon layer 14, which is used as the floating gate, is formed on the tunnel oxide layer);
a semiconductor(Jang, [0007], a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 10.);
and a tunnel oxide layer located between the floating gate layer and the semiconductor layer,(Jang, [0007], a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 10. The silicon substrate 10 has STI regions 16 that define a plurality of active regions therebetween. Floating gates 14 are formed on the tunnel oxide layer 12, [0012], an oxide layer or an oxynitride layer may then be formed on the active region of the semiconductor substrate 10 to form a tunnel oxide layer (i.e., a gate oxide layer) 12.)
wherein in the tunnel oxide layer, a ratio of a minimum thickness of a peripheral area to a maximum thickness of a central area is less than 0.99(Jang, [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 1, [0017], the top surface of the STI isolation layer 16 may be wider than the bottom surface of the STI isolation layer 16 so that the STI isolation layer has a negative vertical inclination. As a result, the first polysilicon layer 14 that is deposited in the portions on the active region between adjacent STI isolation layers 16 has a positive vertical inclination… [0041], The oxidation process may comprise, for example, a wet oxidation, dry oxidation, a radical method, or the like. The exposed upper surface of the first polysilicon layer 104 may oxidize relatively quickly, while the portion of the first polysilicon layer 104 adjacent the seam 105 may oxidize more slowly as the oxidation gas may not be directly introduced into the seams. As a result, the oxidation profile may have an inverse triangle shape.)
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan's Physical unclonable function for security key by enhancing Chang in view of Duncan's systems for introducing controlled non-uniformity in the tunnel oxide layer, including a peripheral-to-central thickness ratio less than 0.99 to ensure increased device-specific variability and resistance to prediction or cloning of PUF responses as taught by Hang in order to enhance security strength and uniqueness of cryptographic key generation.
The motivation is to ensure that the PUF output is derived from inherent, hard-to-replicate physical variations in the memory cell structure, thereby improving resistance to reverse engineering and cloning attacks.
Regarding Claim 2:
The PUF code generating apparatus according to claim 1, Chang in view of Duncan in further view of Jang disclose wherein the first memory cells are NOR flash memory cells(Chang, [0101], The flash memory array 470 can comprise NOR flash, NAND flash, or other types of flash architectures. As a PUF algorithm, as described herein, is executed over a set of memory cells, the PUF block 471).
Regarding Claim 3:
The PUF code generating apparatus according to claim 2, Chang in view of Duncan in further view of Jang disclose wherein the PUF code storage element comprises a plurality of resistive random access memory cells(Chang, [0189], he physical unclonable function can utilize the set of memory cells 189 to produce a data set that can be used to form the key. The data set, upon completion of the execution of the physical unclonable function, can then be copied from the set of memory cells 189 to the particular block 187 reserved or configured for storing the key. The system can produce one or many keys for storage in the particular block 187 reserved for this purpose.),
Regarding Claim 9:
The PUF code generating apparatus according to claim 1, Chang in view of Duncan in further view of Jang disclose further including: a selector circuit, coupled to the PUF code generating element(Chang, [0088], including a host 3300 coupled by a communication link to an integrated circuit 3301 deploying a physical unclonable function using circuitry on the integrated circuit 3301, for security purposes. A variety of technologies for implementing the components of FIG. 33 are described herein in detail.);
and a sense amplifier circuit, coupled between the selector circuit and the PUF code storage element(Chang, [0179], the flash memory array 1610, including word line drivers, sense amplifiers, bit line drivers, voltage sources and other circuits peripheral to the flash memory array. The PUF controller 1630 in this example is connected to the access and bias circuits 1620 of the flash memory array 1610 and includes logic and memory resources used to carry out the processes described herein, including for example some or all of the processes of FIGS. 6, 8, 9, 11 13 and 15.).
Regarding Claim 10:
PUF code generating apparatus according to claim 9, Chang in view of Duncan in further view of Jang disclose further including: a plurality of decoders for addressing a corresponding memory cell in the PUF code storage element which will store a selected PUF code(Chang, [0093], The command decoder 3315 on the guest device decodes the command or sequence of commands, and controls the timing and circuitry needed to generate the PUF key, and to provide the PUF key (2) to the host 3300. Upon receipt of the PUF key at the host, via the interface controller 3302, the PUF key is transferred to key store (3) on the host).
Regarding Claim 8:
The PUF code generating apparatus according to claim 1, Chang in view of Duncan in further view of Jang disclose wherein the PUF code generating element is programmed as a first logic value, and through a data retention loss process, a part of bits of the PUF code generating element randomly changes to a second logic value to generate the PUF code (Duncan, Col. 3, lines 45-55, PUF Design. Specific addresses of cell bits that have retention time failures can be used to construct a PUF in accordance with one embodiment of the invention. FIG. 4 shows an example of data from an array of one column and eight rows. For this example, an address is represented by a row/column combination such as in FIG. 2. A value of the bits at t=To is for all of the bits to store a ‘1’. It can be seen that while all bits start at ‘1’, they eventually transition to ‘0’. If the experiment is halted at t=T1, then data at addresses [ADDR0:ADDR3] can be represented as “1011” and data at addresses [ADDR4:ADDR7] can be represented as “0110”. ).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang’s physical unclonable function for security key by enhancing Chang’s logic to use a physical unclonable function to produce a security key to ensure that a Physically Unclonable Function (PUF) and random number generator capabilities as taught by Duncan to ensure that the PUF to create a unique cryptographic key that is never stored in non-volatile memory and is destroyed when power is removed.
The motivation is to protect against physical attacks, while enhancements address reliability and other vulnerabilities to create a robust security anchor and to generate a unique volatile cryptographic key to increase hardware security within the system.
Regarding Claim 11:
Chang discloses:
A physical unclonable function (PUF) code generating method, configured for a PUF code generating apparatus, wherein the PUF code generating apparatus comprises a PUF code generating element and a PUF code storage element, the PUF code generating method comprising (Chang, [0014], A circuit that generates a PUF is, or includes, a physical entity embodied in a physical structure which produces a code that is easy to evaluate but hard to predict. [0094], A command or set of commands can include a first command (1) which causes transfer (2) of a PUF key from a PUF circuit 3337 to key store 3335. The command or set of commands can identify and address the memory array 3311 to provide the location in a memory array of the key store 3335 or otherwise identify the PUF key store. In some embodiments, the PUF key is modified by glue logic, such as a hash function or other function controlled by the security logic which has complementary logic in the host, before storage in the key store):
and storing the PUF code in the PUF code storage element (Chang, [0094], A command or set of commands can include a first command (1) which causes transfer (2) of a PUF key from a PUF circuit 3337 to key store 3335. The command or set of commands can identify and address the memory array 3311 to provide the location in a memory array of the key store 3335 or otherwise identify the PUF key store. In some embodiments, the PUF key is modified by glue logic, such as a hash function or other function controlled by the security logic which has complementary logic in the host, before storage in the key store),
Chang does not disclose:
configured to have a characteristic of bit data that randomly changes,
programming the flash memory cells to have bit data with as a first logic value, and through a data retention loss process, making a part of bits of the PUF code generating element randomly change to a second logic value, so as to generate a PUF code
Duncan discloses:
configured to have a characteristic of bit data that randomly changes, (Duncan, Col. 1-2, lines 65-67 and 1-2, the bits in a first state with charge on selected bit capacitors; stopping bit refresh for a first predetermined time; re-enabling refresh for a second predetermined time to read and refresh charge on all bits; Col. 5, lines 55-59, the bit cell can be shown as reading a ‘1’ when charge is stored on the capacitor and reading a ‘0’ when the charge as been removed. Once the bit cell capacitor has been charged, it will slowly lose charge through leakage through the capacitor and transistor.)
programming the flash memory cells to have bit data with a first logic value, and through a data retention loss process, making a part of bit data of the randomly change to a second logic value, so as to generate a PUF code(Duncan, PUF Design. Specific addresses of cell bits that have retention time failures can be used to construct a PUF in accordance with one embodiment of the invention. FIG. 4 shows an example of data from an array of one column and eight rows. For this example, an address is represented by a row/column combination such as in FIG. 2. A value of the bits at t=To is for all of the bits to store a ‘1’. It can be seen that while all bits start at ‘1’, they eventually transition to ‘0’. If the experiment is halted at t=T1, then data at addresses [ADDR0:ADDR3] can be represented as “1011” and data at addresses [ADDR4:ADDR7] can be represented as “0110”. ).
Chang in view of Duncan do not disclose:
the PUF code generating element comprising flash memory cells wherein each of the flash memory cells comprises a floating gate layer,
a semiconductor layer
and a tunnel oxide layer located between the floating gate layer and the semiconductor layer
wherein the tunnel oxide layer is fabricated
fabricating through a first process, a second process, or a third process so that a ratio of a minimum thickness of a peripheral area to a maximum thickness of a central area in the tunnel oxide layer is less than 0.99
Jang discloses:
the PUF code generating element comprising flash memory cells wherein each of the flash memory cells comprises a floating gate layer, (Jang, [0005], a flash memory cell of a flash memory device has a structure that includes a floating gate, an interlayer dielectric layer, and a control gate on a semiconductor substrate. [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) [0013], a first polysilicon layer 14, which is used as the floating gate, is formed on the tunnel oxide layer)
a semiconductor layer,(Jang, [0007], a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 10.);
and a tunnel oxide layer located between the floating gate layer and the semiconductor layer (Jang, [0007], a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 10. The silicon substrate 10 has STI regions 16 that define a plurality of active regions therebetween. Floating gates 14 are formed on the tunnel oxide layer 12, [0012], an oxide layer or an oxynitride layer may then be formed on the active region of the semiconductor substrate 10 to form a tunnel oxide layer (i.e., a gate oxide layer) 12.)
wherein the tunnel oxide layer is fabricated(Jang, [0012], FIGS. 2A to 2D are cross-sectional diagrams illustrating a conventional method of fabricating , the HDP oxide layer inside the trench becomes an STI isolation layer 16. As is also shown in FIG. 2A, an oxide layer or an oxynitride layer may then be formed on the active region of the semiconductor substrate 10 to form a tunnel oxide layer (i.e., a gate oxide layer) 12.
fabricating through a first process, a second process, or a third process so that a ratio of a minimum thickness of a peripheral area to a maximum thickness of a central area in the tunnel oxide layer is less than 0.99 (Jang, [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 1, [0017], the top surface of the STI isolation layer 16 may be wider than the bottom surface of the STI isolation layer 16 so that the STI isolation layer has a negative vertical inclination. As a result, the first polysilicon layer 14 that is deposited in the portions on the active region between adjacent STI isolation layers 16 has a positive vertical inclination… [0041], The oxidation process may comprise, for example, a wet oxidation, dry oxidation, a radical method, or the like. The exposed upper surface of the first polysilicon layer 104 may oxidize relatively quickly, while the portion of the first polysilicon layer 104 adjacent the seam 105 may oxidize more slowly as the oxidation gas may not be directly introduced into the seams. As a result, the oxidation profile may have an inverse triangle shape.)
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan's Physical unclonable function for security key by enhancing Chang in view of Duncan's systems for introducing controlled non-uniformity in the tunnel oxide layer, including a peripheral-to-central thickness ratio less than 0.99 to ensure increased device-specific variability and resistance to prediction or cloning of PUF responses as taught by Jang in order to enhance security strength and uniqueness of cryptographic key generation.
The motivation is to ensure that the PUF output is derived from inherent, hard-to-replicate physical variations in the memory cell structure, thereby improving resistance to reverse engineering and cloning attacks.
Regarding Claim 12:
The PUF code generating method according to claim 11, Chang in view of Wang in further view of Duncan disclose wherein the first memory cells are NOR flash memory cells (Chang, [0101], The flash memory array 470 can comprise NOR flash, NAND flash, or other types of flash architectures. As a PUF algorithm, as described herein, is executed over a set of memory cells, the PUF block 471).
Regarding Claim 13:
The PUF code generating method according to claim 12, Chang in view of Wang in further view of Duncan disclose wherein the PUF code storage element comprises a plurality of resistive random access memory cells (Chang, [0189], he physical unclonable function can utilize the set of memory cells 189 to produce a data set that can be used to form the key. The data set, upon completion of the execution of the physical unclonable function, can then be copied from the set of memory cells 189 to the particular block 187 reserved or configured for storing the key. The system can produce one or many keys for storage in the particular block 187 reserved for this purpose.),
Regarding Claim 18:
The PUF code generating method according to claim 11, Chang in view of Duncan in further view of Jhang disclose wherein the data retention loss process includes placing the PUF code generating element in an ambient temperature environment(Chang, [0148], The physical function of programming and erasing floating gate memory cells like that of FIG. 10D induces charge tunneling that changes the charge trapped in the floating gate layer 845. The amount of charge trapped varies according to physical characteristics of each cell, including process variations, temperature variations, voltage variations and the like).
Regarding Claim 19:
The PUF code generating method according to claim 11, Chang in view of Duncan in further view of Jang disclose wherein after the data retention loss process, there is no screen process to screen out an unstable bit(Duncan, Specific addresses of bits that have retention time failures can be used to construct random numbers and PUFs. FI).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Wang’s physical unclonable function for security key by enhancing Chang in view of Wang’s logic to use a physical unclonable function to produce a security key to ensure that a Physically Unclonable Function (PUF) and random number generator capabilities as taught by Duncan to ensure that the PUF to create a unique cryptographic key that is never stored in non-volatile memory and is destroyed when power is removed.
The motivation is to protect against physical attacks, while enhancements address reliability and other vulnerabilities to create a robust security anchor and to generate a unique volatile cryptographic key to increase hardware security within the system.
Regarding Claim 20:
The PUF code generating apparatus according to claim 1, Chang in view of Duncan in further view of Jang disclose wherein the PUF code storage element comprises a plurality of non-volatile memory cells different from the flash memory cells(Chang, [0033], a set of programmable memory cells on an integrated circuit, and logic to generate a data set by processes described herein. [0035], a plurality of flash memory cells, and a controller for executing a PUF and a random number generator to provide a data set using the plurality of flash memory cells.[0036], a plurality of programmable memory cells, and a controller for executing a PUF to provide a data set using the plurality of programmable memory cells)
Claims 4-8 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chang(US Publication No. 20180278418 A1) in view of Duncan(US Patent No. 9425803 B1) in further view of Jang(US Publication No. 20060073653 A1) and in further view of Wang(US Publication No. 2005/110102 A1).
Regarding Claim 4:
Chang in view of Duncan in further view of Jang disclose:
The PUF code generating apparatus according to claim 1…
the ratio of the minimum thickness of the peripheral area to the maximum thickness of the central area is less than 0.99 (Jang, [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 1, [0017], the top surface of the STI isolation layer 16 may be wider than the bottom surface of the STI isolation layer 16 so that the STI isolation layer has a negative vertical inclination. As a result, the first polysilicon layer 14 that is deposited in the portions on the active region between adjacent STI isolation layers 16 has a positive vertical inclination… [0041], The oxidation process may comprise, for example, a wet oxidation, dry oxidation, a radical method, or the like. The exposed upper surface of the first polysilicon layer 104 may oxidize relatively quickly, while the portion of the first polysilicon layer 104 adjacent the seam 105 may oxidize more slowly as the oxidation gas may not be directly introduced into the seams. As a result, the oxidation profile may have an inverse triangle shape.)
the ratio of the minimum thickness of the peripheral area to the maximum thickness of the central area less than 0.99(Jang, [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 1, [0017], the top surface of the STI isolation layer 16 may be wider than the bottom surface of the STI isolation layer 16 so that the STI isolation layer has a negative vertical inclination. As a result, the first polysilicon layer 14 that is deposited in the portions on the active region between adjacent STI isolation layers 16 has a positive vertical inclination… [0041], The oxidation process may comprise, for example, a wet oxidation, dry oxidation, a radical method, or the like. The exposed upper surface of the first polysilicon layer 104 may oxidize relatively quickly, while the portion of the first polysilicon layer 104 adjacent the seam 105 may oxidize more slowly as the oxidation gas may not be directly introduced into the seams. As a result, the oxidation profile may have an inverse triangle shape.)
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan's Physical unclonable function for security key by enhancing Chang in view of Duncan's systems for introducing controlled non-uniformity in the tunnel oxide layer, including a peripheral-to-central thickness ratio less than 0.99 to ensure increased device-specific variability and resistance to prediction or cloning of PUF responses as taught by Jang in order to enhance security strength and uniqueness of cryptographic key generation.
The motivation is to ensure that the PUF output is derived from inherent, hard-to-replicate physical variations in the memory cell structure, thereby improving resistance to reverse engineering and cloning attacks.
Chang in view of Duncan in further view of Jang do not disclose:
wherein the tunnel oxide layer of the flash memory cell is fabricated through a first process so that and the first process comprises
performing an annealing step on the semiconductor layer to form the tunnel oxide layer of a first thickness on the semiconductor layer
and planarizing the tunnel oxide layer to form the tunnel oxide layer of a second thickness on the semiconductor layer, wherein the tunnel oxide layer of the second thickness makes
Wang discloses:
wherein the tunnel oxide layer of the flash memory cell is fabricated through a first process so that and the first process comprises(Wang, [0016], silicon oxide layer and gate oxide layer is in the range about 0.6:1 to about 0.8:1. In some embodiments, where the device is a memory device having buried source/drains, the thickness of the resulting buried drain oxide layer is greater than the thickness of the resulting gate oxide layer.):
performing an annealing step on the semiconductor layer to form the tunnel oxide layer of a first thickness on the semiconductor layer(Wang, [0013], a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure, by forming a first silicon oxide layer and a silicon nitride layer over a substrate, patterning the first silicon oxide layer and the silicon nitride layer, performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently (simultaneously) a second silicon oxide layer. [0014] … a second silicon oxide layer on the exposed surface of the patterned silicon nitride layer, buried drain oxide layers on the buried source/drains, and a gate oxide layer on the metal oxide semiconductor region. );
and planarizing the tunnel oxide layer to form the tunnel oxide layer of a second thickness on the semiconductor layer, wherein the tunnel oxide layer of the second thickness makes(Wang, [0014], a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure, by forming a first oxide layer and a silicon nitride layer over a substrate having a memory region and a metal oxide semiconductor region; patterning the first oxide layer and the silicon nitride layer to form patterned first oxide layers and patterned silicon nitride layers on the memory cell region, [0016], the ratio of the thicknesses of the resulting second silicon oxide layer and gate oxide layer is in the range about 0.6:1 to about 0.8:1. In some embodiments, where the device is a memory device having buried source/drains, the thickness of the resulting buried drain oxide layer is greater than the thickness of the resulting gate oxide layer.)
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan in further view of Jang Physical unclonable function for security key by enhancing Chang in view of Duncan further view of Jang systems for forming a tunnel oxide layer on a semiconductor substrate using a thermal oxidation annealing process and subsequently planarizing the oxide layer to control thickness and surface profile to ensure reliable and controllable formation of memory cell structures suitable for consistent electrical behavior as taught by Wang in order to enhance manufacturability, uniformity, and operational stability of the flash memory cells used in generating PUF responses.
The motivation is to ensure that the oxide layer is properly formed and processed using well-known semiconductor fabrication techniques to achieve predictable device performance and enable effective integration into PUF-based systems.
Regarding Claim 5:
The PUF code generating apparatus according to claim 4, Chang in view of Duncan in further view of Jang and in further viewo of Wang disclose wherein the second thickness of the tunnel oxide layer is between 140 angstroms (Å) and 240 Å(Wang, [0005], a tunnel oxide layer and a silicon nitride layer are first deposited and patterned, and then a top oxide layer is grown on the silicon nitride by wet oxidation. However, the oxidation selectivity of wet oxidation for the substrate and the silicon nitride layer is relatively high, that is, the oxidation rate of wet oxidation for the substrate is far greater than that of the silicon nitride layer. Using a wet oxidation in this manner to form a 100 Å thick top oxide layer).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan in further view of Jang Physical unclonable function for security key by enhancing Chang in view of Duncan further view of Jang systems for forming a tunnel oxide layer on a semiconductor substrate using a thermal oxidation annealing process and subsequently planarizing the oxide layer to control thickness and surface profile to ensure reliable and controllable formation of memory cell structures suitable for consistent electrical behavior as taught by Wang in order to enhance device performance, stability and consistency of the PUF response generated from the memory cells.
The motivation is to ensure that the oxide thickness is chosen from a result effective variable range known to produce predictable electrical behavior in semiconductor memory structures.
Regarding Claim 6:
Chang in view of Duncan in further view of Jang disclose:
The PUF code generating apparatus according to claim 1…
the ratio of the minimum thickness of the peripheral area to the maximum thickness of the central area is less than 0.99 (Jang, [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 1, [0017], the top surface of the STI isolation layer 16 may be wider than the bottom surface of the STI isolation layer 16 so that the STI isolation layer has a negative vertical inclination. As a result, the first polysilicon layer 14 that is deposited in the portions on the active region between adjacent STI isolation layers 16 has a positive vertical inclination… [0041], The oxidation process may comprise, for example, a wet oxidation, dry oxidation, a radical method, or the like. The exposed upper surface of the first polysilicon layer 104 may oxidize relatively quickly, while the portion of the first polysilicon layer 104 adjacent the seam 105 may oxidize more slowly as the oxidation gas may not be directly introduced into the seams. As a result, the oxidation profile may have an inverse triangle shape.)
make the ratio of the minimum thickness of the peripheral area to the maximum thickness of the central area less than 0.99 (Jang, [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 1, [0017], the top surface of the STI isolation layer 16 may be wider than the bottom surface of the STI isolation layer 16 so that the STI isolation layer has a negative vertical inclination. As a result, the first polysilicon layer 14 that is deposited in the portions on the active region between adjacent STI isolation layers 16 has a positive vertical inclination… [0041], The oxidation process may comprise, for example, a wet oxidation, dry oxidation, a radical method, or the like. The exposed upper surface of the first polysilicon layer 104 may oxidize relatively quickly, while the portion of the first polysilicon layer 104 adjacent the seam 105 may oxidize more slowly as the oxidation gas may not be directly introduced into the seams. As a result, the oxidation profile may have an inverse triangle shape.)
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan's Physical unclonable function for security key by enhancing Chang in view of Duncan's systems for introducing controlled non-uniformity in the tunnel oxide layer, including a peripheral-to-central thickness ratio less than 0.99 to ensure increased device-specific variability and resistance to prediction or cloning of PUF responses as taught by Hang in order to enhance security strength and uniqueness of cryptographic key generation.
The motivation is to ensure that the PUF output is derived from inherent, hard-to-replicate physical variations in the memory cell structure, thereby improving resistance to reverse engineering and cloning attacks.
Chang in view of Duncan in further view of Jang do not disclose:
wherein the tunnel oxide layer of the flash memory cell is fabricated through a second process so that, and the second process comprises
performing ion implantation on the semiconductor layer, and forming a silicon nitride layer
removing a part of the silicon nitride layer
and performing an annealing step on the semiconductor layer to form the tunnel oxide layer on the semiconductor layer and
Wang discloses:
wherein the tunnel oxide layer of the flash memory cell is fabricated through a second process so that, and the second process comprises(Wang, [0041], the top oxide is grown from exposed surfaces of the silicon nitride layer following patterning of the nitride and bottom oxide portions, and as a result the corners, or edges, of the silicon nitride layer as formed in this way are entirely covered by oxide, which wraps around the edges of the silicon nitride layer to contact the adjacent portions of the drain/source oxide):
performing ion implantation on the semiconductor layer, and forming a silicon nitride layer(Wang, [0013], In another general aspect the invention features a method for forming a semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure, by forming a first silicon oxide layer and a silicon nitride layer over a substrate, patterning the first silicon oxide layer and the silicon nitride layer,);
removing a part of the silicon nitride layer(Wang, [0020], a silicon nitride layer covering a portion of the first silicon oxide layer; a second silicon oxide layer fully covering the silicon nitride layer and contacting the first silicon oxide layer; and a gate conducting layer over the second silicon oxide layer.);
and performing an annealing step on the semiconductor layer to form the tunnel oxide layer on the semiconductor layer and (Wang, [0016], the ratio of the thicknesses of the resulting second silicon oxide layer and gate oxide layer is in the range about 0.6:1 to about 0.8:1.).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan in further view of Jang Physical unclonable function for security key by enhancing Chang in view of Duncan further view of Jang systems for forming a tunnel oxide layer on a semiconductor substrate using a thermal oxidation annealing process and subsequently planarizing the oxide layer to control thickness and surface profile to ensure reliable and controllable formation of memory cell structures suitable for consistent electrical behavior as taught by Wang in order to enhance manufacturability, uniformity, and operational stability of the flash memory cells used in generating PUF responses.
The motivation is to ensure that the oxide layer is properly formed and processed using well-known semiconductor fabrication techniques to achieve predictable device performance and enable effective integration into PUF-based systems.
Regarding Claim 7:
Chang in view of Duncan in further view of Jang disclose:
The PUF code generating apparatus according to claim 1…
the ratio of the minimum thickness of the peripheral area to the maximum thickness of the central area is less than 0.99 (Jang, [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 1, [0017], the top surface of the STI isolation layer 16 may be wider than the bottom surface of the STI isolation layer 16 so that the STI isolation layer has a negative vertical inclination. As a result, the first polysilicon layer 14 that is deposited in the portions on the active region between adjacent STI isolation layers 16 has a positive vertical inclination… [0041], The oxidation process may comprise, for example, a wet oxidation, dry oxidation, a radical method, or the like. The exposed upper surface of the first polysilicon layer 104 may oxidize relatively quickly, while the portion of the first polysilicon layer 104 adjacent the seam 105 may oxidize more slowly as the oxidation gas may not be directly introduced into the seams. As a result, the oxidation profile may have an inverse triangle shape.)
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan's Physical unclonable function for security key by enhancing Chang in view of Duncan's systems for introducing controlled non-uniformity in the tunnel oxide layer, including a peripheral-to-central thickness ratio less than 0.99 to ensure increased device-specific variability and resistance to prediction or cloning of PUF responses as taught by Jang in order to enhance security strength and uniqueness of cryptographic key generation.
The motivation is to ensure that the PUF output is derived from inherent, hard-to-replicate physical variations in the memory cell structure, thereby improving resistance to reverse engineering and cloning attacks.
Chang in view of Duncan in further view of Jang do not disclose:
wherein the tunnel oxide layer of the flash memory cell is fabricated through a third process so that, and the third process comprises: forming the tunnel oxide layer of a thickness less than 95 angstroms on the semiconductor layer
Wang discloses:
wherein the tunnel oxide layer of the flash memory cell is fabricated through a third process so that, and the third process comprises: forming the tunnel oxide layer of a thickness less than 95 angstroms on the semiconductor layer(Wang, [0035], Memory cells are to be formed in the first region, and logic devices are to be formed in the second region. In a step 104, a tunnel oxide layer 210 is formed over the first and second regions 206, 208 (FIG. 2B). In a step 104, a layer of silicon nitride 212 is deposited over the tunnel oxide layer 210 (FIG. 2C). In a step 108, the layer of silicon nitride is oxidized to form a top oxide layer 214, consuming an upper portion of the silicon nitride layer and resulting in a silicon nitride layer 213 of reduced thickness (FIG. 2D)…).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan in further view of Jang Physical unclonable function for security key by enhancing Chang in view of Duncan further view of Jang systems for forming a tunnel oxide layer on a semiconductor substrate using a thermal oxidation annealing process and subsequently planarizing the oxide layer to control thickness and surface profile to ensure reliable and controllable formation of memory cell structures suitable for consistent electrical behavior as taught by Jang in order to enhance manufacturability, uniformity, and operational stability of the flash memory cells used in generating PUF responses.
The motivation is to ensure that the oxide layer is properly formed and processed using well-known semiconductor fabrication techniques to achieve predictable device performance and enable effective integration into PUF-based systems.
Regarding Claim 14:
Chang in view of Wang in further view of Duncan disclose:
The PUF code generating method according to claim 11…
wherein the tunnel oxide layer of the second thickness makes the ratio of the minimum thickness of the peripheral area to the maximum thickness of the central area less than 0.99(Jang, [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 1, [0017], the top surface of the STI isolation layer 16 may be wider than the bottom surface of the STI isolation layer 16 so that the STI isolation layer has a negative vertical inclination. As a result, the first polysilicon layer 14 that is deposited in the portions on the active region between adjacent STI isolation layers 16 has a positive vertical inclination… [0041], The oxidation process may comprise, for example, a wet oxidation, dry oxidation, a radical method, or the like. The exposed upper surface of the first polysilicon layer 104 may oxidize relatively quickly, while the portion of the first polysilicon layer 104 adjacent the seam 105 may oxidize more slowly as the oxidation gas may not be directly introduced into the seams. As a result, the oxidation profile may have an inverse triangle shape.)
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan's Physical unclonable function for security key by enhancing Chang in view of Duncan's systems for introducing controlled non-uniformity in the tunnel oxide layer, including a peripheral-to-central thickness ratio less than 0.99 to ensure increased device-specific variability and resistance to prediction or cloning of PUF responses as taught by Hang in order to enhance security strength and uniqueness of cryptographic key generation.
The motivation is to ensure that the PUF output is derived from inherent, hard-to-replicate physical variations in the memory cell structure, thereby improving resistance to reverse engineering and cloning attacks.
Chang in view of Wang in further view of Duncan do not disclose:
wherein the first process comprises: performing an annealing step on the semiconductor layer to form the tunnel oxide layer of a first thickness on the semiconductor layer
and planarizing the tunnel oxide layer to form the tunnel oxide layer of a second thickness on the semiconductor layer,
Wang discloses:
wherein the first process comprises: performing an annealing step on the semiconductor layer to form the tunnel oxide layer of a first thickness on the semiconductor layer (Wang, [0013], a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure, by forming a first silicon oxide layer and a silicon nitride layer over a substrate, patterning the first silicon oxide layer and the silicon nitride layer, performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently (simultaneously) a second silicon oxide layer. [0014] … a second silicon oxide layer on the exposed surface of the patterned silicon nitride layer, buried drain oxide layers on the buried source/drains, and a gate oxide layer on the metal oxide semiconductor region. );
and planarizing the tunnel oxide layer to form the tunnel oxide layer of a second thickness on the semiconductor layer, (Wang, [0014], a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure, by forming a first oxide layer and a silicon nitride layer over a substrate having a memory region and a metal oxide semiconductor region, [0016], the ratio of the thicknesses of the resulting second silicon oxide layer and gate oxide layer is in the range about 0.6:1 to about 0.8:1. In some embodiments, where the device is a memory device having buried source/drains, the thickness of the resulting buried drain oxide layer is greater than the thickness of the resulting gate oxide layer.).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan in further view of Jang Physical unclonable function for security key by enhancing Chang in view of Duncan further view of Jang systems for forming a tunnel oxide layer on a semiconductor substrate using a thermal oxidation annealing process and subsequently planarizing the oxide layer to control thickness and surface profile to ensure reliable and controllable formation of memory cell structures suitable for consistent electrical behavior as taught by Wang in order to enhance manufacturability, uniformity, and operational stability of the flash memory cells used in generating PUF responses.
The motivation is to ensure that the oxide layer is properly formed and processed using well-known semiconductor fabrication techniques to achieve predictable device performance and enable effective integration into PUF-based systems.
Regarding Claim 15:
The PUF code generating method according to claim 14, Chang in view of Duncan in further view of Jang and in further view of Wang disclose wherein the second thickness of the tunnel oxide layer is between 140 angstroms (Å) and 240 Å (Wang, [0005], a tunnel oxide layer and a silicon nitride layer are first deposited and patterned, and then a top oxide layer is grown on the silicon nitride by wet oxidation. However, the oxidation selectivity of wet oxidation for the substrate and the silicon nitride layer is relatively high, that is, the oxidation rate of wet oxidation for the substrate is far greater than that of the silicon nitride layer. Using a wet oxidation in this manner to form a 100 Å thick top oxide layer).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan in further view of Jang Physical unclonable function for security key by enhancing Chang in view of Duncan further view of Jang systems for forming a tunnel oxide layer on a semiconductor substrate using a thermal oxidation annealing process and subsequently planarizing the oxide layer to control thickness and surface profile to ensure reliable and controllable formation of memory cell structures suitable for consistent electrical behavior as taught by Wang in order to enhance manufacturability, uniformity, and operational stability of the flash memory cells used in generating PUF responses.
The motivation is to ensure that the oxide layer is properly formed and processed using well-known semiconductor fabrication techniques to achieve predictable device performance and enable effective integration into PUF-based systems.
Regarding Claim 16:
Chang in view of Wang in further view of Duncan disclose:
The PUF code generating method according to claim 11…
that the ratio of the minimum thickness of the peripheral area to the maximum thickness of the central area is less than 0.99(Jang, [0007], the flash memory cell has a stacked gate structure, in which a tunnel oxide layer 12 (for F-N tunneling) is formed on a silicon substrate 1, [0017], the top surface of the STI isolation layer 16 may be wider than the bottom surface of the STI isolation layer 16 so that the STI isolation layer has a negative vertical inclination. As a result, the first polysilicon layer 14 that is deposited in the portions on the active region between adjacent STI isolation layers 16 has a positive vertical inclination… [0041], The oxidation process may comprise, for example, a wet oxidation, dry oxidation, a radical method, or the like. The exposed upper surface of the first polysilicon layer 104 may oxidize relatively quickly, while the portion of the first polysilicon layer 104 adjacent the seam 105 may oxidize more slowly as the oxidation gas may not be directly introduced into the seams. As a result, the oxidation profile may have an inverse triangle shape.)
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan's Physical unclonable function for security key by enhancing Chang in view of Duncan's systems for introducing controlled non-uniformity in the tunnel oxide layer, including a peripheral-to-central thickness ratio less than 0.99 to ensure increased device-specific variability and resistance to prediction or cloning of PUF responses as taught by Jang in order to enhance security strength and uniqueness of cryptographic key generation.
The motivation is to ensure that the PUF output is derived from inherent, hard-to-replicate physical variations in the memory cell structure, thereby improving resistance to reverse engineering and cloning attacks.
Chang in view of Duncan in further view of Jang do not disclose:
wherein the second process comprises: performing ion implantation on the semiconductor layer, and forming a silicon nitride layer
Wang discloses:
wherein the second process comprises: performing ion implantation on the semiconductor layer, and forming a silicon nitride layer (Wang, [0013], In another general aspect the invention features a method for forming a semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure, by forming a first silicon oxide layer and a silicon nitride layer over a substrate, patterning the first silicon oxide layer and the silicon nitride layer,);
removing a part of the silicon nitride layer (Wang, [0020], a silicon nitride layer covering a portion of the first silicon oxide layer; a second silicon oxide layer fully covering the silicon nitride layer and contacting the first silicon oxide layer; and a gate conducting layer over the second silicon oxide layer.);
and performing an annealing step on the semiconductor layer to form the tunnel oxide layer on the semiconductor layer so (Wang, [0013], a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure, by forming a first silicon oxide layer and a silicon nitride layer over a substrate, patterning the first silicon oxide layer and the silicon nitride layer, performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently (simultaneously) a second silicon oxide layer. [0014] … a second silicon oxide layer on the exposed surface of the patterned silicon nitride layer, buried drain oxide layers on the buried source/drains, and a gate oxide layer on the metal oxide semiconductor region. )
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan in further view of Jang Physical unclonable function for security key by enhancing Chang in view of Duncan further view of Jang systems for forming a tunnel oxide layer on a semiconductor substrate using a thermal oxidation annealing process and subsequently planarizing the oxide layer to control thickness and surface profile to ensure reliable and controllable formation of memory cell structures suitable for consistent electrical behavior as taught by Wang in order to enhance manufacturability, uniformity, and operational stability of the flash memory cells used in generating PUF responses.
The motivation is to ensure that the oxide layer is properly formed and processed using well-known semiconductor fabrication techniques to achieve predictable device performance and enable effective integration into PUF-based systems.
Regarding Claim 17:
Chang in view of Duncan in further view of Jang disclose:
The PUF code generating method according to claim 11…
Chang in view of Duncan in further view of Jang do not disclose:
wherein the third process comprises: forming the tunnel oxide layer of a thickness less than 95 angstroms on the semiconductor layer
Wang discloses:
wherein the third process comprises: forming the tunnel oxide layer of a thickness less than 95 angstroms on the semiconductor layer (Wang, [0035], Memory cells are to be formed in the first region, and logic devices are to be formed in the second region. In a step 104, a tunnel oxide layer 210 is formed over the first and second regions 206, 208 (FIG. 2B). In a step 104, a layer of silicon nitride 212 is deposited over the tunnel oxide layer 210 (FIG. 2C). In a step 108, the layer of silicon nitride is oxidized to form a top oxide layer 214, consuming an upper portion of the silicon nitride layer and resulting in a silicon nitride layer 213 of reduced thickness (FIG. 2D)…).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Chang in view of Duncan in further view of Jang Physical unclonable function for security key by enhancing Chang in view of Duncan further view of Jang systems for forming a tunnel oxide layer on a semiconductor substrate using a thermal oxidation annealing process and subsequently planarizing the oxide layer to control thickness and surface profile to ensure reliable and controllable formation of memory cell structures suitable for consistent electrical behavior as taught by Wang in order to enhance the PUF response generated from the flash memory cells.
The motivation is to ensure that reducing oxide thickness increases tunneling probability and variability in electrical behavior, which enhances entropy generating in memory based PUF systems
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/MAYASA A. SHAAWAT/Examiner, Art Unit 2433
/JEFFREY C PWU/Supervisory Patent Examiner, Art Unit 2433
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