DETAILED ACTION
This action is responsive to the following communications: the Application filed February 27, 2024, and the information disclosure statement (IDS) filed February 27, 2024.
Claims 1-20 are pending. Claims 1, 6 and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 27, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang et al. (CN 104078078 A; cited on IDS filed 2/27/24, and of Record with English translation) in view of Sudo (US 2006/0267076).
Regarding independent claims 1 and 6, Wang et al. teach an SFGT storage array (FIG. 1), comprising a true semi-floating gate array (102, para. 0022: 102 comprising … to half-floating gate memory), a reference semi-floating gate array (103, para. 0023: 103 comprises … the fourth reference level half-floating gate) and a sense amplifier (101, para. 0021: sensitive amplifying circuit 101), wherein
the true semi-floating gate array comprises a plurality of true semi-floating gate storage units (para. 0022: … 102 comprising … to half-floating gate memory), a plurality of first bit lines and a plurality of first word lines, each of the plurality of first bit lines intersects with each of the plurality of first word lines for performing operation on one of the plurality of true semi-floating gate storage units, each of the plurality of first bit lines is connected to a first input end of the sense amplifier, each of the plurality of true semi-floating gate storage units is located at an intersection position of one of the plurality of first bit lines and one of the plurality of first word lines, and the reference semi-floating gate array (para. 0023: 103 comprises … the fourth reference level half-floating gate) comprises a plurality of second bit lines, each of the plurality of second bit lines is connected to a second input end of the sense amplifier.
Wang’s semi-floating gate array (FIG. 1) does not explicitly disclose the claimed memory array structure includes several a pair of true and reference singles that control a differential sense amplifier circuit.
Sudo teaches the deficiencies in FIG. 2 and accompanying disclosure, i.e.,
a true array (20a) a plurality of first bit lines and a plurality of first word lines, each of the plurality of first bit lines intersects with each of the plurality of first word lines for performing operation on one of the plurality of true semi-floating gate storage units (see primary reference Wang’s figure 1, half-floating gate memory), each of the plurality of first bit lines is connected to a first input end of the sense amplifier (11), each of the plurality of true semi-floating gate storage units (see primary reference Wang’s figure 1, half-floating gate memory) is located at an intersection position of one of the plurality of first bit lines and one of the plurality of first word lines, and the reference array (30a) comprises a plurality of second bit lines, each of the plurality of second bit lines is connected to a second input end of the sense amplifier (11) (see FIG. 2 and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Sudo to the teaching of Wang et al. such that a memory, as taught by Wang et al., utilizes a matrix memory structure that controls differential sense amplifier, as taught by Sudo, for the purpose of enabling high speed memory reading operations (see Sudo, Abstract), further these conventional technology are well established in the art of the memory devices.
Regarding claim 2, Wang et al. and Sudo, as combined, teach the limitations of claim 1.
Wang et al. further teach the claimed semi-floating gate array (e.g., para. 0022: 102 comprising … to half-floating gate memory).
Sudo further teaches the reference semi-floating gate array comprises a plurality of reference semi-floating gate storage units and a reference word line, each of the plurality of second bit lines intersects with the reference word line for performing operation on one of the plurality of reference semi-floating gate storage units, each of the reference semi-floating gate storage unit is located at an intersection position of one of the plurality of second bit lines and the reference word line (see FIG. 2 and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Sudo combined with Wang for the same purpose of enhancing data read operations.
Regarding claim 3, Wang et al. and Sudo, as combined, teach the limitations of claim 2.
By combining Sudo’s memory structure with Wang’s half-floating gate further teach the true semi-floating gate array, the reference semi-floating gate array and the sense amplifier correspond each other one-by-one (see Sudo’s FIGS. 2-3 and accompanying disclosure).
Regarding claim 4, Wang et al. and Sudo, as combined, teach the limitations of claim 3.
By combining Sudo’s memory structure with Wang’s half-floating gate further teach the plurality of first bit lines in the true semi-floating gate array drive to a first reference semi-floating gate array and a second reference semi-floating gate array on either side of the true semi-floating gate array respectively (see Sudo’s FIGS. 2-3 and accompanying disclosure).
Regarding claim 5, Wang et al. and Sudo, as combined, teach the limitations of claim 4.
By combining Sudo’s memory structure with Wang’s half-floating gate further teach the true semi-floating gate array corresponds to the first reference semi-floating gate array and the second reference semi-floating gate array; the ones numbered as odd serial numbers of the plurality of first bit lines comprised in the true semi-floating gate array are connected to a first input end of a first sense amplifier, the ones numbered as even serial numbers of the plurality of first bit lines comprised in the true semi-floating gate array are connected to a first input end of a second sense amplifier; each of a plurality of second bit lines comprised in the first reference semi-floating gate array is connected to a second input end of the first sense amplifier; and each of a plurality of second bit lines comprised in the second reference semi-floating gate array is connected to a second input end of the second sense amplifier (see Sudo’s FIGS. 2-3 and accompanying disclosure).
Regarding claim 7, Wang et al. and Sudo, as combined, teach the limitations of claim 6.
Sudo further teaches a circuit module, connected to the column-decoding module, the row-decoding module and the logic control module, and configured to supply voltages for the column-decoding module, the row-decoding module and the logic control module (FIG 2 and accompanying disclosure; further claimed row and column decoders in a memory device is a well-known technology).
Regarding claims 8-11, Wang et al. and Sudo, as combined, teach the limitations of claim 6.
Sudo further teaches a data transmission path, connected to the column-decoding module and the logic control module; and an address input interface, connected to the row-decoding module and the logic control module; a command input interface, connected to the logic control module; and a data input/output interface, connected to the data transmission path (FIG 2 and accompanying disclosure).
Further claimed row and column decoders including a date path is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize row and column decoders including a data I/O path in memory circuits because these conventional technology are well established in the art of the memory devices.
Regarding claim 12, Wang et al. and Sudo, as combined, teach the limitations of claim 6.
By combining Sudo’s memory structure with Wang’s half-floating gate further teach the reference semi-floating gate array comprises a plurality of reference semi-floating gate storage units and a reference word line, each of the plurality of second bit lines intersects with the reference word line for performing operation on one of the plurality of reference semi-floating gate storage units, each of the reference semi-floating gate storage unit is located at an intersection position of one of the plurality of second bit lines and the reference word line (see Sudo’s FIGS. 2-3 and accompanying disclosure).
Regarding claim 13, Wang et al. and Sudo, as combined, teach the limitations of claim 12.
By combining Sudo’s memory structure with Wang’s half-floating gate further teach the true semi-floating gate array, the reference semi-floating gate array and the sense amplifier correspond each other one-by-one (see Sudo’s FIGS. 2-3 and accompanying disclosure).
Regarding independent claim 14, Wang et al. teach a data-reading method performed by an SFGT storage array (FIG. 1) comprising a true semi-floating gate array (102, para. 0022: 102 comprising … to half-floating gate memory), a reference semi-floating gate array (103, para. 0023: 103 comprises … the fourth reference level half-floating gate) and a sense amplifier (101, para. 0021: sensitive amplifying circuit 101), wherein the method comprises:
obtaining a first voltage variation value of a first target bit line corresponding to a target true semi-floating gate storage unit (para. 0022: … 102 comprising … to half-floating gate memory) through which a first target word line passes, the first target word line being one of a plurality of first word lines comprised in the true semi-floating gate array; obtaining a second voltage variation value of a second target bit line in the reference semi-floating gate array (para. 0023: 103 comprises … the fourth reference level half-floating gate); controlling the sense amplifier to amplify the first voltage variation value and obtain a first amplified voltage variation value, and to amplify the second voltage variation value to obtain a second amplified voltage variation value; and reading, based on the first amplified voltage variation value and the second amplified voltage variation value, a target storage value of the target true semi-floating gate storage unit.
Wang’s semi-floating gate array (FIG. 1) does not explicitly disclose the claimed memory array structure includes several a pair of true and reference singles that control a differential sense amplifier circuit.
Sudo teaches the deficiencies in FIG. 2 and accompanying disclosure, i.e.,
obtaining a first voltage variation value of a first target bit line (see FIG. 2: MGB bit line voltages varied by selected word lines) corresponding to a target true semi-floating gate storage unit through which a first target word line passes, the first target word line being one of a plurality of first word lines comprised in the true semi-floating gate array ;
obtaining a second voltage variation value of a second target bit line (see FIG. 2: RGB bit line voltages varied by selected word lines) in the reference semi-floating gate array;
controlling the sense amplifier (FIG. 2: 11) to amplify the first voltage variation value and obtain a first amplified voltage variation value, and to amplify the second voltage variation value to obtain a second amplified voltage variation value; and
reading, based on the first amplified voltage variation value and the second amplified voltage variation value, a target storage value of the target true semi-floating gate storage unit (see FIG. 2 and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Sudo to the teaching of Wang et al. such that a memory, as taught by Wang et al., utilizes a matrix memory structure that controls differential sense amplifier, as taught by Sudo, for the purpose of enabling high speed memory reading operations (see Sudo, Abstract), further these conventional technology are well established in the art of the memory devices.
Further, regarding method claim 14, MPEP 2112.02(I) instructs examiners, “Under the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).” Here, the applied prior art product is identical to applicant’s disclosed product, and therefore is assumed, in accordance with MPEP 2112.02(I), to inherently perform the claimed process.
Regarding claim 15, Wang et al. and Sudo, as combined, teach the limitations of claim 14.
By combining Sudo’s memory structure with Wang’s half-floating gate further teach the operation of obtaining the second voltage variation value of the second target bit line in the reference semi-floating gate array comprises: obtaining the second voltage variation value of the second target bit line corresponding to a reference semi-floating gate storage unit through which a reference word line in the reference semi-floating gate array passes (see Sudo’s FIGS. 2-3 and accompanying disclosure).
Regarding claim 16, Wang et al. and Sudo, as combined, teach the limitations of claim 14.
By combining Sudo’s memory structure with Wang’s half-floating gate further teach before the operation of obtaining the first voltage variation value of the first target bit line corresponding to the target true semi-floating gate storage unit through which the first target word line passes, the method further comprises: receiving a data-reading instruction; selecting, based on the data-reading instruction, the first target word line and a reference word line; the operation of obtaining the first voltage variation value of the first target bit line corresponding to the target true semi-floating gate storage unit through which the first target word line passes comprises: after a preset time interval, obtaining the first voltage variation value of the first target bit line corresponding to the target true semi-floating gate storage unit through which the first target word line passes (see Sudo’s FIGS. 2-3 and accompanying disclosure).
Regarding claim 17, Wang et al. and Sudo, as combined, teach the limitations of claim 14.
By combining Sudo’s memory structure with Wang’s half-floating gate further teach the operation of obtaining the second voltage variation value of the second target bit line in the reference semi-floating gate array comprises: obtaining a preset second voltage variation value from the sense amplifier connected to the second target bit line (see Sudo’s FIGS. 2-3 and accompanying disclosure).
Regarding claim 18, Wang et al. and Sudo, as combined, teach the limitations of claim 14.
By combining Sudo’s memory structure with Wang’s half-floating gate further teach the operation of reading, based on the first amplified voltage variation value and the second amplified voltage variation value, the target storage value of the target true semi-floating gate storage unit comprises: reading, in response to the first amplified voltage variation value being greater than the second amplified voltage variation value, the target storage value of the target true semi-floating gate storage unit as a first storage value; reading, in response to the first amplified voltage variation value being less than the second amplified voltage variation value, the target storage value of the target true semi-floating gate storage unit as a second storage value; wherein the first storage value is different from the second storage value (see Sudo’s FIGS. 2-3 and accompanying disclosure, i.e., differential sensing scheme of the voltages varied from main cell array and the voltages varied from reference cell array).
Regarding claims 19-20, Wang et al. and Sudo, as combined, teach the limitations of claim 14.
By combining Sudo’s memory structure with Wang’s half-floating gate further teach the reference semi-floating gate array comprises a plurality of reference semi-floating gate storage units and a reference word line, each of the plurality of second bit lines intersects with the reference word line for performing operation on one of the plurality of reference semi-floating gate storage units, each of the reference semi-floating gate storage unit is located at an intersection position of one of the plurality of second bit lines and the reference word line; and the true semi-floating gate array, the reference semi-floating gate array and the sense amplifier correspond each other one-by-one (see Sudo’s FIG. 2 and accompanying disclosure).
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825