DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 7/24/2026. Claims 1, 2, 4-11 & 13-20 are pending in this application. Claims 3 & 12 are canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1, 2, 4-9, 11 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2023/0062026) in view of Sharma et al. (US 2024/0222271).
Re claim 1, Yu teaches, under BRI, in view of Figs. 9A, 15A, 16A, G, J, 19 & 20, [0016, 0020, 0029, 0033, 0037, 0051, 0056], a three-dimensional semiconductor device comprising:
-a first active region (under 147) on a substrate (102) (Fig. 15A), including a lower channel pattern (106b) and a lower source/drain pattern (146) connected to the lower channel pattern (106b), the lower channel pattern (106b) including a plurality of lower semiconductor patterns (106b) stacked and spaced apart from each other in a first direction (vertical or z-axis) that is perpendicular to an upper surface of the substrate (102), and the plurality of lower semiconductor patterns (106b) including a first semiconductor pattern (bottom 106b), the first semiconductor pattern (bottom 106b) of the plurality of lower semiconductor patterns being closest to the substrate (102);
-a second active region (above 147) stacked on the first active region (Fig. 15A), including an upper channel pattern (106a) and an upper source/drain pattern (149) connected to the upper channel pattern (106a);
-a lower gate electrode (first gate electrode 171) on the lower channel pattern (106b) (Fig. 16G); and
-a lower insulating pattern (e.g., consider gate dielectric 166 under isolation 174) under the first semiconductor pattern (bottom 106b) in the first direction (z-axis) (Fig. 16G),
wherein the lower gate electrode (171) (Fig. 16G) includes
a first portion (left portion) adjacent to a first sidewall of the lower insulating pattern (166) and extending in the first direction (z-axis) from an upper surface to a bottom surface of the lower gate electrode (171),
a second portion (right portion) adjacent to a second sidewall of the lower insulating pattern (166) and extending in the first direction (z-axis) from the upper surface to the bottom surface of the lower gate electrode (171), the second sidewall facing the first sidewall in a second direction (horizontal or y-axis) which is perpendicular to the first direction (z-axis), and
a third portion (bottom portion) in contact with a bottom surface of the lower insulating pattern (166) and extending from the first portion to the second portion in the second direction (y-axis).
Note: in contact # directly or physically contact. And oxide layer 159 around 106b can be considered as lower insulating pattern.
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Yu does not teach an inner electrode of the lower gate electrode is interposed between the first semiconductor pattern and the lower insulating pattern in the first direction, and wherein the first semiconductor pattern is spaced apart from the lower insulating pattern in the first direction by the inner electrode.
Sharma teaches, Fig. 1D, [0036, 0038], an inner electrode (indicated) of the lower gate electrode (126) is interposed between the first semiconductor pattern (consider lower 122) and the lower insulating pattern (124) in the first direction (vertical), and wherein the first semiconductor pattern (consider 122) is spaced apart from the lower insulating pattern (124) in the first direction by the inner electrode (indicated).
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As taught by Sharma, one of ordinary skill in the art would utilize & modify the above teaching to obtain an inner electrode of the lower gate electrode is interposed between the first semiconductor pattern and the lower insulating pattern in the first direction, and wherein the first semiconductor pattern is spaced apart from the lower insulating pattern in the first direction by the inner electrode as claimed, because it aids in achieving an integrated circuit, having routing across layer of channel structures, with improved performance and increased bandwidth.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Sharma in combination Yu due to above reason.
Re claim 2, Yu teaches, under BRI, Fig. 16G, wherein a width of the lower gate electrode (171) in the second direction (y-axis) decreases from the bottom surface of the lower gate electrode (171) to the bottom surface of the lower insulating pattern (consider 166 around 106b) (e.g., width from ends of 171 vs. width of 171 between 106b & side 166).
Re claim 4, Yu teaches, Fig. 16J, [0060], an upper gate electrode (186) on the upper channel pattern (106a), wherein the upper gate electrode (186) and the lower gate electrode (171) are spaced apart from each other in the first direction (z-axis) with a separation pattern (isolation layer 184) therebetween.
Re claim 5, Yu teaches, under BRI, Fig. 16G, wherein a width of each of the first portion and the second portion (left & right portions between 106b & side of 166) increases as the first portion and the second portion approach the bottom surface of the lower insulating pattern (161 or 166) (e.g. width of 171 changing from side to lower surface of lower 166)
Re claim 6, Yu teaches, Fig 20, [0071], a lower gate contact (236) electrically connected to the third portion (of 171).
Re claim 7, Yu teaches, under BRI, Figs. 19-20, [0071], a lower active contact (234) electrically connected (within the formed device) to the lower source/drain pattern (146), wherein an upper surface of the lower active contact (234) is positioned at a higher level than an upper surface of the lower gate contact (236).
Re claim 8, Yu teaches, Fig. 16G, [0051], a gate insulating layer (166 around 106b) between the upper surface and both sidewalls of the lower insulating pattern (consider interfacial layer 159) and the lower gate electrode (171).
Re claim 9, Yu teaches, Fig. 16G, wherein a maximum width of the lower gate electrode (171) is greater than a maximum width of the lower insulating pattern (consider 166 around 106b).
Re claim 11, Yu teaches, under BRI, in view of Figs. 9A, 15A, 16A, G, J, 19 & 20, [0016, 0020, 0029, 0033, 0037, 0051, 0056], a three-dimensional semiconductor device comprising:
-a first active region (under 147) on a substrate (102) (Fig. 15A), including a lower channel pattern (106b) and a lower source/drain pattern (146) connected to the lower channel pattern (106b), the lower channel pattern including a plurality of lower semiconductor patterns (106b) stacked and spaced apart from each other in a first direction (z-axis), and the plurality of lower semiconductor patterns including a first semiconductor pattern (bottom106b), the first semiconductor pattern (bottom 106b) of the plurality of lower semiconductor patterns being closes to the substrate (102);
-a second active region (above 147) stacked on the first active region (Fig. 15A), including an upper channel pattern (106a) and an upper source/drain pattern (149) connected to the upper channel pattern (106a);
-a lower gate electrode (171) on the lower channel pattern, the lower gate electrode includes an inner electrode (extends under bottom 106b) below the first semiconductor pattern (bottom 106b) in the first direction (z-axis) (Fig. 16G); and
-a lower insulating pattern (portion of 166 around 106b) under the first semiconductor pattern (lower 106b) in the first direction (z-axis) (Fig. 16G),
wherein the first semiconductor pattern (106b) is spaced apart (by 159) from the lower insulating pattern (166) in the first direction (z-axis), and
wherein the lower gate electrode (171) surrounds an upper surface, both sidewalls, and bottom surface of the lower insulating pattern (166).
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Yu does not teach the inner electrode is interposed between the first semiconductor pattern and the lower insulating pattern in the first direction, and wherein the first semiconductor pattern is spaced apart from the lower insulating pattern in the first direction by the inner electrode.
Sharma teaches, Fig. 1D, [0036, 0038], the inner electrode (indicated) is interposed between the first semiconductor pattern (consider lower 122) and the lower insulating pattern (124) in the first direction (vertical), and wherein the first semiconductor pattern (consider 122) is spaced apart from the lower insulating pattern (124) in the first direction by the inner electrode (indicated).
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As taught by Sharma, one of ordinary skill in the art would utilize & modify the above teaching to obtain the inner electrode interposed between the first semiconductor pattern and the lower insulating pattern in the first direction, and wherein the first semiconductor pattern is spaced apart from the lower insulating pattern in the first direction by the inner electrode as claimed, because it aids in achieving an integrated circuit, having routing across layer of channel structures, with improved performance and increased bandwidth.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Sharma in combination Yu due to above reason.
Re claim 13, Yu teaches, Fig. 16J, an upper gate electrode (186) on the upper channel pattern (106a), wherein the upper gate electrode (186) and the lower gate electrode (171) are spaced apart from each other in the first direction with a separation pattern (184) therebetween.
Re claim 14, Yu teaches, Fig. 16G, wherein a width of the lower gate electrode (171) increases as the lower gate electrode (171) approaches to bottom surface of the lower insulating pattern (166) (e.g. increase around the curve of 166).
Re claim 15, Yu teaches, Fig. 20, [0071], a lower gate contact (234) electrically connected to the lower gate electrode (171).
Re claim 16, Yu teaches, under BRI, in view of Figs. 9A, 15A, 16A, G, J, 19 & 20, [0016, 0020, 0029, 0033, 0037, 0051, 0056, 0071], a three-dimensional semiconductor device comprising:
-a first active region (under 147) on a substrate (102) (Fig. 15A), including a lower channel pattern (106b) and a lower source/drain pattern (146) connected to the lower channel pattern (106b), the lower channel pattern including a plurality of lower semiconductor patterns (106b) stacked and spaced apart from each other in a first direction (z-axis), and the plurality of lower semiconductor patterns including a first semiconductor pattern (bottom 106b), the first semiconductor pattern (bottom 106b) of the plurality of lower semiconductor pattens (106b) being closest to the substrate (102);
-a second active region (above 147) stacked on the first active region (Fig. 15A), including an upper channel pattern (106a) and an upper source/drain pattern (149) connected to the upper channel pattern (106a);
-a lower gate electrode (171) on the lower channel pattern (106b), the lower gate electrode (171) including an inner electrode (extends under 106b) below the first semiconductor pattens in the first direction (z-axis);
-a lower gate contact (234) electrically connected to the lower gate electrode (171) (Fig. 20); and
-a lower insulating pattern (lower 159 around 106b) under the first semiconductor pattern (bottom 106b) (Fig. 16G),
wherein a level of a bottom surface of the lower gate electrode (171) is lower than a level of a bottom surface of the lower insulating pattern (e.g. 159 around 106b), and
wherein a maximum width of the lower gate electrode (171) is greater than a maximum width of the lower insulating pattern (159 around 106b) (Fig. 16G).
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Yu does not teach the inner electrode is interposed between the first semiconductor pattern and the lower insulating pattern in the first direction, and wherein the first semiconductor pattern is spaced apart from the lower insulating pattern in the first direction by the inner electrode.
Sharma teaches, Fig. 1D, [0036, 0038], the inner electrode (indicated) is interposed between the first semiconductor pattern (consider lower 122) and the lower insulating pattern (124) in the first direction (vertical), and wherein the first semiconductor pattern (consider 122) is spaced apart from the lower insulating pattern (124) in the first direction by the inner electrode (indicated).
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As taught by Sharma, one of ordinary skill in the art would utilize & modify the above teaching to obtain the inner electrode interposed between the first semiconductor pattern and the lower insulating pattern in the first direction, and wherein the first semiconductor pattern is spaced apart from the lower insulating pattern in the first direction by the inner electrode as claimed, because it aids in achieving an integrated circuit, having routing across layer of channel structures, with improved performance and increased bandwidth.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Sharma in combination Yu due to above reason.
Re claim 17, Yu teaches, Fig. 16G, wherein the lower gate electrode (171) surrounds an upper surface, both sidewalls, and the bottom surface of the lower insulating pattern (lower 159).
Re claim 18, Yu teaches, Fig. 16J, an upper gate electrode (186) on the upper channel pattern (106a), wherein the upper gate electrode (186) and the lower gate electrode (171) are spaced apart from each other in the first direction with a separation pattern (184) therebetween.
Re claim 19, Yu teaches, Fig. 16G, a gate insulating layer (166) between upper surface and both sidewalls of the lower insulating pattern (159) and the lower gate electrode (171).
Re claim 20, Yu teaches, under BRI, Fig. 16G, wherein a width of the lower gate electrode (171) in the second direction (y-axis) decreases from the bottom surface of the lower gate electrode (171) to the bottom surface of the lower insulating pattern (159) (e.g., width from ends of 171 vs. width of 171 between 106b & side 166).
3. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu as modified by Sharma as applied to claim 1 above, and further in view of Thomas et al. (US 2023/0037957).
The teachings of Yu/Sharma have been discussed above.
Re claim 10, Yu/Sharma does not explicitly teach wherein the lower source/drain pattern has a first conductivity type, and the upper source/drain pattern has a second conductivity type different from the first conductivity type.
Thomas teaches PMOS source/drain regions (109, 110) and NMOS source/drain regions (113, 114) (Fig. 1a, [0035]).
As taught by Thomas, one of ordinary skill in the art would utilize & modify the above teaching to obtain the lower source/drain pattern has a first conductivity type, and the upper source/drain pattern has a second conductivity type different from the first conductivity type as claimed, because it aids in achieving desired stacked configuration of a CMOS with improved performance.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Thomas in combination Yu/Sharma due to above reason.
Response to Arguments
4. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. (US 2014/0001441, Figs. 1A-D) discloses nanodevice with internal spacers & gate electrode around nanowire stack.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/3/26
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