Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 14 objected to because of the following informalities: instances of "...electrically connected to one of the upper inductor and the lower inductor..." and "...electrically connected to the other of the upper inductor and the lower inductor." are likely mean to read "the upper inductor or the lower inductor" instead of "and". Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, and 9-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Osada et al. (US Patent No. 12,387,868), hereinafter referred to as Osada.
Regarding claim 1, Osada teaches a semiconductor device comprising: a first semiconductor chip in which a transistor is not formed (Figs. 1 & 2, transformer chip 6; Col. 5, line 9 – Col. 7, line 11), wherein the first semiconductor chip comprising: a semiconductor substrate (Figs. 1-6, semiconductor substrate 26; Col. 7, lines 25-30); a multilayer wiring layer formed on the semiconductor substrate, the multilayer wiring layer comprising: a first layer; and a second layer disposed over the first layer; a lower inductor formed in the first layer of the multilayer wiring layer; an upper inductor formed in the second layer of the multilayer wiring layer, the upper inductor overlapping the lower inductor in plan view (Figs. 3-6, insulating layer laminated structure 27, lower coil 20, upper coil 21, low voltage wiring 24, through wiring 51, lead-out wiring 52; Col. 5, line 9 - Col. 12, line 36 and Col. 20, lines 45-55); and a conductive pattern formed in at least one layer of the multilayer wiring layer, wherein the conductive pattern continuously surrounds the lower inductor and the upper inductor in plan view (Figs. 3-6, high voltage region 36, low voltage region 46, intermediate region 48, capacitor 80; Col. 5, line 9 - Col. 13, line 27).
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Regarding claim 2, Osada further teaches the conductive pattern comprising: a first conductive pattern formed in one layer of the multilayer wiring layer; and a second conductive pattern formed in another layer of the multilayer wiring layer (Figs. 3-6 & 11, insulating layers 28, capacitor 80; Col. 5, line 9 - Col. 13, line 27 and Col. 13, lines 51-56).
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Regarding claim 5, Osada further teaches the first semiconductor chip comprising a sealing ring continuously surrounding the conductive pattern in plan view (Figs. 3-6, shield layer 69; Col. 5, lines 9 – Col. 12, line 36).
Regarding claim 9, Osada further teaches a shortest distance between the conductive pattern and the upper inductor is equal to or greater than a distance between the lower inductor and the upper inductor (Fig. 6, distance L1, thickness L2; Col. 12 line 64 - Col. 13, line 3).
Regarding claim 10, Osada further teaches a dielectric film in contact with the conductive pattern is formed over or under the conductive pattern, and wherein a thickness of the conductive pattern is equal to or greater than a thickness of the dielectric film (Fig. 6, insulating layers 28, interlayer insulating film 30, capacitor 80, Col. 5, lines 9 - Col. 13, line 27).
Regarding claim 11, Osada further teaches a dielectric film is formed between the lower inductor and the upper inductor, and wherein the conductive pattern continuously surrounds a portion of the dielectric film overlapping the lower inductor and the upper inductor in plan view (Figs. 3-6, lower coil 20, upper coil 21, insulating layers 28, interlayer insulating film 30, capacitor 80, Col. 5, lines 9 - Col. 13, line 27).
Regarding claim 12, Osada further teaches a second semiconductor chip different from the first semiconductor chip, wherein the second semiconductor chip is electrically connected to the upper inductor or the lower inductor (Figs. 1 & 2, controller chip 5, low voltage pads 13, lower coil 20; Col. 5 line 9 - Col. 7, line 11).
Regarding claim 13, Osada further teaches the second semiconductor chip including a first transmitting circuit or a first receiving circuit, wherein a transistor used for the first transmitting circuit or the first receiving circuit is formed in the second semiconductor chip, and wherein the first transmitting circuit or the first receiving circuit is electrically connected to the upper inductor or the lower inductor (Figs. 1 & 2, controller chip 5, low voltage pads 13, lower coil 20, transistors Tr1 and Tr2; Col. 5 line 9 - Col. 7, line 11).
Regarding claim 14, Osada further teaches a third semiconductor chip different from the first semiconductor chip and the second semiconductor chip, wherein the third semiconductor chip includes a second transmitting circuit or a second receiving circuit, wherein a transistor used for the second transmitting circuit or the second receiving circuit is formed in the third semiconductor chip, wherein the first transmitting circuit or the first receiving circuit is electrically connected to one of the upper inductor or the lower inductor, and wherein the second transmitting circuit or the second receiving circuit is electrically connected to the other of the upper inductor or the lower inductor (Figs. 1 & 2, driver chip 7, high voltage pads 14, upper coil 21; Col. 5 line 9 - Col. 7, line 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 4, and 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Osada in view of Uchida et al. (Pub. No. US 20180308795 A1), hereinafter referred to as Uchida.
Regarding claim 3, Osada teaches the semiconductor device of claim 2. Osada further teaches a conductor pattern comprised of a plurality of electrode plates which are arranged continuously in the vertical direction such that there are no gaps along the lamination direction of the insulating layer laminated structure (Figs. 6 & 7, capacitor 80, electrode plates 87, insulating laminated structure 27; Col. 12, lines 46-58) and that layers in the device can be connected using plugs (Fig. 6, vias 38, 55, 56, 57, 59; Col. 5, line 9 - Col. 12, line 36). However, Osada does not explicitly teach the first conductive pattern and the second conductive pattern being connected to each other via a plurality of plugs.
However, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Osada to connect the conductive patterns of Osada via a plurality of plugs as connecting two or more layer of a device using plugs is well known and conventional in the art and could be used instead of connecting the conductive patterns by stacking the electrode plates. For the purpose of compatibility with existing manufacturing process, electrical performance, or manufacturing costs.
Regarding claim 4, Osada further teaches the second conductive pattern being formed over the first conductive pattern (Figs. 3-6 & 11, insulating layers 28, capacitor 80; Col. 5, line 9 - Col. 13, line 27 and Col. 13, lines 51-56). Osada also teaches the conductor pattern being formed continuously in the vertical direction (Figs. 6 & 7, capacitor 80, electrode plates 87, insulating laminated structure 27; Col. 12, lines 46-58). However, Osada does not teach the second conductive pattern and the plurality of plugs being configured by the same film.
Uchida teaches forming the conductive pattern by patterning a conductive film (Figs. 6-8, conductive film CF, conductive pattern CP; ¶77-80).
Osada and Uchida are analogous art as they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Osada to incorporate the teachings of Uchida such that the conductive pattern is formed using a conductive film, and wherein the second conductive pattern and the plurality of plugs are configured by the same film. For the purpose of having a more compact size, reducing manufacturing costs, and simplifying manufacturing.
Regarding claim 6, Osada further teaches the conductive pattern being surrounded by a first border line continuously surrounding the lower inductor and the upper inductor in plan view and a second border line continuously surrounding the first border line in plan view, and wherein the first border line has a curved line (Figs. 3-6, high voltage region 36, low voltage region 46, intermediate region 48, capacitor 80; Col. 5, line 9 - Col. 13, line 27). However, Osada does not teach the conductive pattern being configured by a conductive film.
Uchida teaches the conductive pattern being configured by a conductive film (Figs. 6-8, conductive film CF, conductive pattern CP; ¶77-80).
Osada and Uchida are analogous art as they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Osada to incorporate the teachings of Uchida such that the conductive pattern is configured by a conductive film. For the purpose of having a more compact size, reducing manufacturing costs, and simplifying manufacturing.
Regarding claim 7, Osada further teaches a compressive stress film capable of preventing generation of large curvature deformations of the semiconductor wafer (Col. 15, line 5 - 62). However, Osada does not explicitly teach the conductive pattern has a function of suppressing a warp of the semiconductor substrate. Though it is worth noting that the compressive stress film is introduced in the embodiment that removes the conductive pattern, which would suggest that the conductive pattern does have the function of suppressing a warp of the semiconductor substrate that has to be compensated for by the compressive stress film when the conductive pattern is removed.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Osada such that the conductive pattern has a function of suppressing a warp of the semiconductor substrate either in combination with or in lieu of the compressive stress film. For the purpose of preventing damage to the device from warpage of the substrate.
Regarding claim 8, Osada further teaches a compressive stress film capable of preventing generation of large curvature deformations of the semiconductor wafer (Col. 15, line 5 - 62). However, Osada does not explicitly teach each of the plurality of plugs has a function of suppressing a warp of the semiconductor substrate. Though it is worth noting that the compressive stress film is introduced in the embodiment that removes the conductive pattern, which would suggest that the conductive pattern does have the function of suppressing a warp of the semiconductor substrate that has to be compensated for by the compressive stress film when the conductive pattern is removed.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Osada such that the conductive pattern has plugs and those plugs have a function of suppressing a warp of the semiconductor substrate either in combination with or in lieu of the compressive stress film. For the purpose of preventing damage to the device from warpage of the substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN ALEXANDER TUTTLE whose telephone number is (571)272-7055. The examiner can normally be reached Monday - Friday, 9 am - 5 pm ET.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./ Examiner, Art Unit 2897
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