Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the second crystal structure is identical to the first crystal structure" in line 7. There is insufficient antecedent basis for this limitation in the claim. (The applicant’s amendment of claim 6 on 7/24/26 removed “having a first crystal structure” and “having a second crystalline structure”, so claim 6 is not clear what limitations “the second crystal structure” and “the first crystal structure” are referring to.
MPEP 2173 [R-10.2019] discloses “[i]t is of utmost importance that patents issue with definite claims that clearly and precisely inform persons skilled in the art of the boundaries of protected subject matter. Therefore, claims that do not meet this standard must be rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph as indefinite” (bolding and underline of “must be” added).
The applicant could delete the limitation "the second crystal structure is identical to the first crystal structure" in order to remove the 112(b) rejection.
Allowable Subject Matter
Claims 1-5, 8-13 are allowable.
Claim 6-7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance as the prior art of record fails to teach or suggest: a first transistor arranged on a substrate; and a second transistor arranged on the first transistor, wherein the first transistor comprises: a first gate electrode arranged on the substrate; a first insulating film arranged on the first gate electrode; a first oxide semiconductor layer arranged on the first insulating film, having a region overlapping the first gate electrode, and having a polycrystalline structure; a second insulating film arranged on the first oxide semiconductor layer; and a second gate electrode arranged on the second insulating film, wherein the second transistor comprises: a third gate electrode arranged on the second insulating film; a third insulating film arranged on the third gate electrode; a second oxide semiconductor layer arranged on the third insulating film and having a region overlapping the third gate electrode; a fourth insulating film arranged on the second oxide semiconductor layer; and a fourth gate electrode arranged on the fourth insulating film (claims 1-5, 8-13).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US 2022/0302239) disclose a display device with thin film transistors, but fails to explicitly disclose a first transistor arranged on a substrate; and a second transistor arranged on the first transistor, wherein the first transistor comprises: a first gate electrode arranged on the substrate; a first insulating film arranged on the first gate electrode; a first oxide semiconductor layer arranged on the first insulating film, having a region overlapping the first gate electrode, and having a polycrystalline structure; a second insulating film arranged on the first oxide semiconductor layer; and a second gate electrode arranged on the second insulating film, wherein the second transistor comprises: a third gate electrode arranged on the second insulating film; a third insulating film arranged on the third gate electrode; a second oxide semiconductor layer arranged on the third insulating film and having a region overlapping the third gate electrode; a fourth insulating film arranged on the second oxide semiconductor layer; and a fourth gate electrode arranged on the fourth insulating film.
Chiu et al. (US 2023/0268355) disclose TFT FETs at different levels but fails to explicitly disclose a first transistor arranged on a substrate; and a second transistor arranged on the first transistor, wherein the first transistor comprises: a first gate electrode arranged on the substrate; a first insulating film arranged on the first gate electrode; a first oxide semiconductor layer arranged on the first insulating film, having a region overlapping the first gate electrode, and having a polycrystalline structure; a second insulating film arranged on the first oxide semiconductor layer; and a second gate electrode arranged on the second insulating film, wherein the second transistor comprises: a third gate electrode arranged on the second insulating film; a third insulating film arranged on the third gate electrode; a second oxide semiconductor layer arranged on the third insulating film and having a region overlapping the third gate electrode; a fourth insulating film arranged on the second oxide semiconductor layer; and a fourth gate electrode arranged on the fourth insulating film.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRADLEY SMITH/Primary Examiner, Art Unit 2817
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