DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on 7/6/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2023/0337558, hereinafter, Chang) in view of LIU (US 2020/0328186, hereinafter, Liu.)
In regard to claims 1 and 12, in fig. 1, Chang discloses a semiconductor device SD10, comprising:
a first semiconductor device, including:
a substrate,
a memory array 240 disposed above the substrate and below a frontside surface of the first semiconductor device,
a plurality of source region contact (SRC) nodes disposed under the memory array, and
a plurality of diodes (or transistors, para [0014]) disposed in the substrate, each of the plurality of HV diodes being connected to corresponding one of the plurality of SRC nodes; and
a second semiconductor device (above layer 190) including a plurality of complementary-metal-oxide semiconductor (CMOS) devices (part of the memory 250), each of the plurality of CMOS devices being connected to, through a backside surface of the second semiconductor device and the frontside surface of the first semiconductor device, corresponding bond pad of the memory array,
wherein fusion bonding exists between the backside surface of the second semiconductor device and the frontside surface of the first semiconductor device. The fusion bonding is considered to be a product-by-process limitation and has not given a patentable weight in a product claim.
Chang, however, does not clearly mention the diodes or the transistors are power diode/transistor (level of doping concentration.)
Liu, in fig. 10, discloses an analogous semiconductor device 1000 including semiconductor devices, MOSFET, for example, formed in the substrate. Liu further teaches the semiconductor are high power devices, the high popping concentration (described in para [0068].)
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed ot have high doping concentration as taught in order to adjust the electron mobility within the device. It is common in the art.
Regarding claims 2-3, 11, and 14, the combination as mentioned above discloses wherein each of the plurality of HV diodes comprises a lightly doped region disposed under a frontside surface of the substrate of the first semiconductor device and a heavily doped region disposed within the lightly doped region (para [0068].)
Regarding claims 4-6 and 15, the combination further discloses wherein the lightly doped region and the heavily doped region of each of the plurality of HV diodes comprises N type dopant materials including Phosphorus, Arsenic, and/or Antimony (Chang’s para [0046].)
Regarding claims 7-8, Chang further comprising a dielectric layer disposed above the substrate and under the plurality of SRC nodes; and a plurality of interconnection contacts connecting the plurality of HV diodes to corresponding SRC nodes, wherein the plurality of interconnection contacts pass through the dielectric layer. Fig. 1.
Regarding claim 9, the combination further discloses wherein each of the plurality of interconnection contacts is connected to the heavily doped region of corresponding one of the plurality of HV diodes. Liu’s fig. 10 and Chang’s fig. 1.
Regarding claim 10, t6he above combination discloses all of the claimed limitations including the dimensions of the doping areas, except the exact values as currently claimed. However, the dimensions in this case are considered a non-critical feature and may be altered during a routine of manufacturing. Furthermore, the dimensions as disclosed would allow the device to function the same as the currently claimed device.
Regarding claim 13, the combination further discloses wherein the plurality of diodes of the first semiconductor device are connected, through the plurality of SRC nodes and the bonding interface, to corresponding CMOS devices of the second semiconductor device. Chang’s fig. 1.
14. (Original) The semiconductor device of claim 13, wherein each of the plurality of HV diodes of the first semiconductor device comprises a N type lightly doped region disposed under corresponding one of the plurality of SRC nodes, and a N type heavily doped region disposed within the N type lightly doped region.
15. (Original) The semiconductor device of claim 14, further comprising a plurality of P type heavily doped regions disposed between the plurality of SRC nodes and the backside surface of the first semiconductor device, wherein the plurality of P type heavily doped regions comprise dopant materials including Boron and/or Gallium.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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/NATHAN W HA/Primary Examiner, Art Unit 2814
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