CTNF 18/588,460 CTNF 101647 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Invention A in the reply filed on 05/12/2026 is acknowledged. 08-25 AIA Applicant's election with traverse of Group I in the reply filed on 05/12/2026 is acknowledged. The traversal is on the ground(s) that the package may have anyone of the wiring structures . This is not found persuasive because the argument does not explain why the species are not independent or distinct. The wring structure of Fig. 1 does not pertain to species Group I . The requirement is still deemed proper and is therefore made FINAL. 08-06 AIA Claim s 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method of Invention B , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/12/2026 . Claims 4-7, 15, 16 are withdrawn from further consideration as being drawn to nonelected species of Group II or III. Please note that, even though applicant requested for claim 4 and claim 15 to be examined they will not be examined since they relate to species Group II and/or III, because claim 15 requires “metal layer is in contact with the side surface of the via” and since applicant’s traversal arguments were found unpersuasive because they do not address that why the species are not considered independent or distinct . Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. 23-19 AIA Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3, 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masaya Nagano Takizawa et al. (US 20240404978 A1) using the (JP 2024173293 A) machine translation hereinafter referred to as “Taki”, and further in view of Toshihiko Ito et al. (JP 2008135762 A) hereinafter referred to as Ito . Regarding Claim 1 Taki teaches A wiring structure (Fig. 23 and 24) comprising: a wiring layer (122) including a wiring pad (122 and 110); an insulating layer (172) on the wiring layer and covering the wiring layer; a connection pad (142) on (in contact with) the insulating layer; and a via (141and 142) passing through the insulating layer and connecting the wiring pad and the connection pad, wherein the wiring pad includes a first metal layer (122) and a second layer (110) on (above vertically) the first metal layer, and a bottom surface of the via (bottom of 141 is in contact with 122) abuts the first metal layer, and the second metal layer surrounds a side surface of the via and is adjacent to the bottom surface of the via.(Fig 23 and 24) Taki does not teach The second layer as a second metal layer Ito teaches a wiring layer with a a second metal layer (Fig. 3 element 28A) on (in contact with) a first metal layer (25) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Taki such that the second layer is a second metal layer, as described in Ito because the layer 110 in Taki and the wedge 28A-28L in Ito were both known to improve adhesion and the simple substitution of material from one known element for anther to obtain the same predictable result would be obvious. (Taki Page 4, And Ito Page 7) Regarding Claim 2 Taki in view of Ito teaches The wiring structure of claim 1, Taki further teaches wherein the insulating layer fills a space (Fig. 24 element 143) between the second metal layer and the side surface of the via. Regarding Claim 3 Taki in view of Ito teaches The wiring structure of claim 2, Taki further teaches PNG media_image1.png 241 452 media_image1.png Greyscale wherein D1 is a diameter of the bottom surface of the via (141 and 142), (Fig.2, see diagram) D2 is a difference between an inside diameter of the second metal layer and a diameter of the via at a level of a boundary of the first metal layer and the second metal layer, (see diagram) and D2/D1 is equal to or smaller than 0.05. (Taki teaches that the width of the gap is a result effective variable and it would be obvious to find a width that maximizes the filling efficiency of insulating material into the D2 gap. Page 4) Regarding Claim 8 Taki in view of Ito teaches The wiring structure of claim 1, Ito further teaches the second metal layer being made by electrolytic plating wherein the second layer is metal Taki further teaches that a nickel layer made by electrolytic plating is a viable surface treatment due to its ability to avoid chipping therefore one could have the second metal layer containing nickel (Ni) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Taki in view of Ito such that the second metal layer contains Nickel, as described in Ito and Taki because the modification of the Nickel material avoids chipping (Ito page 9 And Taki page 4 and 6) Regarding Claim 9 Taki in view of Ito Teaches The wiring structure of claim 1, Taki further teaches PNG media_image2.png 370 764 media_image2.png Greyscale wherein the wiring layer further includes a wiring pattern (element 122 Fig 24. see diagram) including the first metal layer (122) , and the first metal layer in the wiring pattern is covered by the insulating layer.(see diagram) Regarding Claim 10 Taki in view of Ito Teaches The wiring structure of claim 1, Taki further teaches wherein the wiring layer (122 and 110) and the insulating layer (172) are among a plurality of wiring layers and a plurality of insulating layers (the wiring and insulating layers of 120) , respectively, the wiring pad (122) is in an uppermost wiring layer of the plurality of wiring layers (see Fig 24), and the wiring pad is covered by an uppermost insulating layer of the plurality of insulating layers such that the insulating layer is the uppermost insulating layer of the plurality of insulating layers. (see Fig 24) 07-21-aia AIA Claim (s) 11-14, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun Tae Lee et al. (US 20220037276 A1) Hereinafter referred to as “Lee” , and further in view of Taki in further view of Ito . Regarding Claim 11 Lee teaches PNG media_image3.png 427 933 media_image3.png Greyscale A semiconductor package (Fig 15) comprising: a first semiconductor package including a first wiring structure (see diagram), a first semiconductor chip (120) on the first wiring structure and electrically connected to the first wiring structure, a sealing material (130a) on the first wiring structure and encapsulating the first semiconductor chip (Fig 15), a second wiring structure (see diagram) on the sealing material, and conductive posts (117) passing through the sealing material and electrically connecting the first wiring structure and the second wiring structure together; and a second semiconductor package on the first semiconductor package and including a second semiconductor chip (161), wherein the second wiring structure includes a wiring layer (150) including a wiring pad (142), an insulating layer (161r) on the wiring layer and covering the wiring layer, a connection pad(161s) on the insulating layer, and a via (161s to142) passing through the insulating layer and connecting the wiring pad and the connection pad together, the wiring pad (142) includes a first metal layer(142 Para [0081]), a bottom surface of the via (bottom of 161s is in contact with 142) is in contact with the first metal layer, the connection pad (161s) electrically connects the second semiconductor package(161) and the second wiring structure together.(Fig 15) Lee does not teach the second metal layer of the wiring pad and therefore is not relied upon the teach a second metal layer on the first metal layer, and the second metal layer surrounds a side surface of the via adjacent to the bottom surface, Taki does teach the second wiring structure with a second layer (not metal) the second wiring structure (Fig 23 and 24) includes a wiring layer (122) including a wiring pad(122 and 110), an insulating layer (172) on the wiring layer and covering the wiring layer, a connection pad (142) on (in contact with) the insulating layer, and a via (141 and 142) passing through the insulating layer and connecting the wiring pad and the connection pad together, the wiring pad includes a first metal layer (122) and a second layer (110) on (above) the first metal layer, a bottom surface of the via (bottom of 141 is in contact with 122) is in contact with the first metal layer, the second metal layer surrounds a side surface of the via adjacent to the bottom surface (Fig 23 and 24), and the connection pad electrically connects the second semiconductor package (170) and the second wiring structure together. (Fig 23 and 24) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lee such that the wiring structure has a second layer of the wiring pad, as described in Taki because the modification allows for increased adhesion between layers. (Taki Page 4 ) Lee in view of Taki does not teach the second metal layer being metal Ito teaches a wiring layer with a a second metal layer (Fig. 3 element 28A) on (in contact with) a first metal layer (25) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lee in view of Taki such that the second layer is a second metal layer, as described in Ito because the layer 110 in Taki and the wedge 28A-28L in Ito were both known to improve adhesion and the simple substitution of material from one known element for anther to obtain the same predictable result would be obvious. (Taki Page 4 And Ito page 7) Regarding Claim 12 Lee in view of Taki in view of Ito teaches The semiconductor package of claim 11, Lee further teaches further comprising: a conductive bump (161b) between the second semiconductor package(161) and the connection pad. (161s, see fig 15) Regarding Claim 13 Lee in view of Taki in view of Ito teaches The semiconductor package of claim 11, Lee further teaches wherein the first semiconductor chip (120) includes an application processor (AP) chip (Para [0065]), and the second semiconductor chip(161) includes a memory chip (Para [0084]). Regarding Claim 14 Lee in view of Taki in view of Ito teaches The semiconductor package of claim 11, Lee does not teach a second metal layer and therefore is not relied upon to teach wherein the insulating layer fills a space between the second metal layer and the side surface of the via. Taki does teach a second layer (not metal) wherein the insulating layer(172) fills a space between the second layer(110) and the side surface of the via.(140) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lee in view of Taki in view of Ito such that the insulating layer material fills the space between the second layer and the via, as described in Taki because the modification allows for improved adhesion (Taki Page 4) Lee in view of Taki does not teach The second layer being a second metal layer Ito teaches a wiring layer with a a second metal layer (Fig. 3 element 28A) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Lee in view of Taki in view of Ito such that the second layer is a second metal layer, as described in Ito because the layer 110 in Taki and the wedge 28A-28L in Ito were both known to improve adhesion and the simple substitution of material from one known element for anther to obtain the same predictable result would be obvious. (Taki Page 4 And Ito page 7) Regarding Claim 17 Lee in view of Taki in view of Ito teaches The semiconductor package of claim 11, Lee further teaches wherein the second wiring structure (Fig 15 element150) further includes a wiring pattern, the wiring pattern includes the first metal layer (142), and the first metal layer included in the wiring pattern is covered by the insulating layer(161r) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. SHIMIZU; Noriyoshi (US 20160020163 A1), Lee; Dae Hee (US 20230012399 A1), Yamashita; Soichi (US 8314491 B2) , Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Friday, 9:00a.m. - 5:00p.m. ET.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAIME LYNN SPRENGER/ Examiner, Art Unit 2893 /SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893 Application/Control Number: 18/588,460 Page 2 Art Unit: 2893 Application/Control Number: 18/588,460 Page 3 Art Unit: 2893 Application/Control Number: 18/588,460 Page 4 Art Unit: 2893 Application/Control Number: 18/588,460 Page 5 Art Unit: 2893 Application/Control Number: 18/588,460 Page 6 Art Unit: 2893 Application/Control Number: 18/588,460 Page 7 Art Unit: 2893 Application/Control Number: 18/588,460 Page 8 Art Unit: 2893 Application/Control Number: 18/588,460 Page 9 Art Unit: 2893 Application/Control Number: 18/588,460 Page 10 Art Unit: 2893 Application/Control Number: 18/588,460 Page 11 Art Unit: 2893
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