Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/22/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20190157244 A1) in view of Lee (US 20120038045 A1).
Regarding claim 1, Hong teaches, in FIG. 1, a semiconductor package comprising a first “semiconductor chip” 120 having a front side and a backside that is opposite the front side, the first semiconductor chip having “connection terminals” (constituting a frontside wiring structure) 163 disposed on the front side and “connection terminals” (constituting a backside wiring structure) 162 disposed on the back side and a first “TSV” (through via) 124 electrically connected to the front and backside wiring structures, “buffer semiconductor chip” (second semiconductor chip) 110 which is disposed on the backside of the first semiconductor chip and includes a second “TSV” (through via) 114, and a third “semiconductor chip” 150 disposed on the front side of the first semiconductor chip, wherein the first semiconductor chip is electrically coupled to the second semiconductor chip via the first and semiconductor vias and the backside wiring structure (i.e., the first semiconductor chip is configured to receive power through the second through-via). Hong further teaches, in paragraph 0063: “the thickness t1 of the buffer semiconductor chip 110 may be different from the thickness t2 of the first semiconductor chip 120.”
Hong does not explicitly teach that the second semiconductor chip has a greater thickness than the first semiconductor chip.
Lee teaches, in FIG. 14, a semiconductor package comprising a first semiconductor chip 23, a second semiconductor chip 21 disposed on the backside of the first semiconductor chip, and a third semiconductor chip 25 which is disposed at the frontside of the first semiconductor chip. Additionally, paragraph 0085 states: “The [semiconductor chip] 21 may have a third thickness T3. The third thickness T3 may be greater than the second thickness T2 and less than the first thickness T1.” Wherein the second thickness T2 corresponds to the thickness of the first semiconductor chip and the second semiconductor chip (see paragraph 0069).
It would have been obvious to one having ordinary skill in the art to modify the device taught by Hong such that the second semiconductor chip is thicker than the first semiconductor chip, as taught by Lee. One having ordinary skill in the art is motivated to do so because, for example, doing so “. . . may decrease fault rates of reliability due to a mismatch of a thermal expansion coefficient and a thermal budget, and a production yield may be improved” (Lee, paragraph 0036).
Regarding claim 3, Hong further teaches, in FIG. 1, that the third semiconductor chip is electrically connected to the first chip (through vias 124, 134, and 144, as well as “connection terminals” which make up wiring structures 162, 163, 164, and 165), and is therefore configured to receive power through the first semiconductor chip.
Regarding claim 4, Hong further teaches, in paragraph 0062: “A thickness t2 of the first semiconductor chip 120, a thickness t3 of the second semiconductor chip 130, and a thickness t4 of the third semiconductor chip 140 may be the same as (i.e., equal to) one another.”
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20190157244 A1) in view of Lee (US 20120038045 A1) in further view of Cheng (US 11164853 B1).
Regarding claim 2, Hong further teaches, in paragraph 0066 “the width L2 of the buffer semiconductor chip 110 may be greater than the width L1 of each of the first to third semiconductor chips 120, 130, 140 and the upper semiconductor chip 150. However, embodiments of the present disclosure are not limited thereto.”
Hong does not explicitly teach that the width of the first semiconductor chip is greater than a width of the second semiconductor chip.
Cheng teaches, in FIG. 1, a semiconductor package with a first chip 110, a second chip (“carrier 150 is a silicon chip,” paragraph 14) 150 on the backside of the first chip, and a third chip 120 on the frontside of the first chip. Paragraph 14 also states: “. . . a width of the carrier 150 is greater than the width of the first chip 110 . . .”
It would have been obvious to one having ordinary skill in the art to modify the device taught by Hong and Lee such that the width of the first semiconductor chip is greater than a width of the second semiconductor chip, as taught by Cheng. One having ordinary skill in the art is motivated to do so in order to, for example, grant the first chip a larger surface area, enhancing its thermal dissipation properties, while keeping the overall profile of the chip reduced (by keeping the second chip smaller).
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20190157244 A1) in view of Lee (US 20120038045 A1) in view of Chen (US 20210375819 A1)
Regarding claim 5, as explained above, Hong and Lee teach the limitations of claim 1. Hong further teaches, in FIG. 1, “connection terminals” (first connection pad) disposed on the backside of the first semiconductor chip (making up the back side wiring structure).
They do not teach that the second semiconductor chip has a second connection pad that contacts the first connection pad.
Chen teaches, in FIG. 9, “chips” (first and second semiconductor chips) 46-1 and 46-2 wherein the second chip is disposed on the backside of the first wafer. The first wafer comprises TSVs 26 and “bond pads” (first connection pad) 45 (see FIG. 9) and the second semiconductor chip comprises second connection pads 45 which directly contacts the first connection pad.
It would have been obvious to one having ordinary skill in the art to modify the packaging structure taught by Hong and Lee such that the back side wiring structure of the first semiconductor chip includes a first connection pad, wherein the second semiconductor chip includes a second connection pad, and wherein the first connection pad directly contacts the second connection pad, as taught by Chen. One having ordinary skill in the art is motivated to do so in order to, for example, increase the electrical bonding area, decreasing resistance in the device, and thereby improving thermal and electrical performance.
Regarding claim 6, Chen further teaches, paragraph 0038: “FIG. 10 illustrates the cross-sectional view of reconstructed wafer 102 and the singulated packages 102′ in accordance with some embodiments. These embodiments are similar to the embodiments shown in FIG. 9, except that there may be more tiers of wafers 22 (including 22-1 through 22-m) . . . In accordance with some embodiments, each of integers m and n may be any integer greater than 2, such as 3, 4, . . .” Thus, Chen discloses a third semiconductor chip disposed on the frontside of the first semiconductor chip (46--k, where k is an integer). As shown in FIG. 10, the first semiconductor chip has “bond pads” (first connection pad) 45 disposed on the front side of the first substrate, and a third semiconductor chip (46--(k-1)) which has a second connection pad that directly contacts the second connection pad.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Hong such that third chip comprises a second connection pad which directly contacts the first connection pad. One having ordinary skill in the art is motivated to do so in order to, for example, increase the electrical bonding area, decreasing resistance in the device, and thereby improving thermal and electrical performance.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20190157244 A1) in view of Lee (US 20120038045 A1) in further view of Ohba (US 20220208710 A1).
Regarding claim 7, Hong and Lee do not explicitly teach thicknesses to semiconductor chips.
Ohba teaches, in FIG. 2, a semiconductor stack comprising a first chip 30--(2) and a second chip 30(1) disposed on the backside of the first chip. In FIG. 6, this structure is again shown and paragraph 0069 states: “The minimum thickness of each of the semiconductor chips 30.sub.1 to 30.sub.5 and the minimum thickness of the semiconductor chip 40 may be 4 μm.”
It would have been obvious to one of ordinary skill in the art to modify the package taught by Hong such that the first semiconductor chip has a thickness between 2 to 10 µm, as taught by Ohba. One having ordinary skill in the art is motivated to do so in order to, for example, decrease the size of the device. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20190157244 A1) in view of Lee (US 20120038045 A1) in further view of Nam (US 20220246582 A1).
Regarding claim 8, Nam teaches, in FIG. 1A, a first semiconductor chip 200, and a second semiconductor chip 100 that is disposed on the backside of the first semiconductor chip. Paragraph 0019 states: “The first thickness T1 may range from about 30 μm to about 60 μm.”
It would have been obvious to one having ordinary skill in the art to modify the semiconductor package taught by Hong such that the second semiconductor chip has a thickness between 20 and 100 µm, as taught by Nam. One having ordinary skill in the art is motivated to do so because, for example, doing so strikes a balance between compact size and strength for a lower chip, which has to support the chips above (Nam, bottom of paragraph 0019).
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20190157244 A1) in view of Lee (US 20120038045 A1) in further view of Lo (US 20230061189 A1).
Regarding claim 9, as explained above, Hong and Lee teach the limitations of claim 1. They do not explicitly teach the utility of individual chips.
Lo teaches, in FIG. 5, a semiconductor package with a first semiconductor chip 400 in which “in some embodiments, the functional units of the first stacking chip 400A may cooperate together and provide a logic functionality” (paragraph 064) and a second semiconductor chip 200 in which “the functional units of the first bottom chip 200 may only include core storage circuit such as I/O and clocking circuit” (paragraph 0047), wherein the second semiconductor chip is disposed at a backside of the first semiconductor chip.
It would have been obvious to one having ordinary skill in the art to modify the device taught by Hong such that the first semiconductor chip includes a logic circuit and the second semiconductor chip includes at least one of an input/output circuit and an analog circuit, as taught by Lo. One having ordinary skill in the art is motivated to do so in order to, for example, provide logic functionality to the chip stack, enabling its use in a commercial or consumer electronic device. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 10, Lo further teaches, in FIG. 12, that a third chip 500A may be added to the frontside of the first semiconductor chip, paragraph 0082 states “The third stacking chip 500A may include memory circuits . . .”
It would have been obvious to one having ordinary skill in the art to modify the device taught by Hong such that the third semiconductor chip includes a memory circuit, as taught by Lo. One having ordinary skill in the art is motivated to do so in order to, for example, add a memory functionality to the above mentioned logic functionality, increasing the commercial or consumer utility of the device. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20190157244 A1) in view of Lee (US 20120038045 A1) in further view of Lo (US 20230061189 A1) and You (US 20210167040 A1).
Regarding claim 11, as explained above, Hong, Lee, and Lo teach the limitations of claim 9. They do not teach that the third semiconductor chip is a dummy chip.
You teaches, in FIG. 1, a semiconductor package with a first “integrated circuit chip” (semiconductor chip 220), a second semiconductor chip 210 disposed at the backside of the first semiconductor chip, and a third “dummy chip” 310 disposed at the frontside of the first semiconductor chip.
It would have been obvious to one having ordinary skill in the art to further modify the device taught by Hong such that the third semiconductor chip is a dummy chip, as taught by You. One having ordinary skill in the art is motivated to do so in because, for example, “. . . the second dummy chip 320 may decrease in parasitic capacitance and the semiconductor package 10 may increase in performance . . .” (You, paragraph 0041).
Claim(s) 12 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20190157244 A1) in view of You (US 20210167040 A1).
Regarding claim 12, Hong teaches, in FIG. 1, a semiconductor package comprising a first “semiconductor chip” 120 having a front side and a backside that is opposite the front side, the first semiconductor chip having “connection terminals” (constituting a frontside wiring structure) 163 disposed on the front side and “connection terminals” (constituting a backside wiring structure) 162 disposed on the back side and a first “TSV” (through via) 124 electrically connected to the front and backside wiring structures, “buffer semiconductor chip” (second semiconductor chip) 110 which is disposed on the backside of the first semiconductor chip and includes a second “TSV” (through via) 114, and a third “semiconductor chip” 150 disposed on the front side of the first semiconductor chip, wherein the first semiconductor chip is electrically coupled to the second semiconductor chip via the first and semiconductor vias and the backside wiring structure (i.e., the first semiconductor chip is configured to receive power through the second through-via). Additionally, “molding material” (encapsulant) encapsulates the second semiconductor chip.
Hong does not teach a rewiring structure and does not explicitly teach relative diameters of through-vias.
You teaches, in FIG. 1, (the examiner notes that the following interpretation of You is divergent front the interpretation used in claim 11) a first semiconductor chip 310 and a second semiconductor chip 210 disposed at the backside of the first semiconductor chip, as well as a third semiconductor chip, 400, stacked above the first. “Internal line” 110 (connected to “external terminals” 130), and “package substrate” 100 constitute a rewiring structure disposed on the second chip. The first semiconductor chip has a first through-via 315 and the second semiconductor chip has a second “through structure” (through-via) 225, and a diameter of the first through-via is less than a diameter of the second through-via.
It would have been obvious to one having ordinary skill in the art to modify the package taught by Hong such that the package comprises a rewiring structure on the second semiconductor chip, and that such that the diameter of the first through-via is less than a diameter of the second through-via. One having ordinary skill in the art is motivated to add a rewiring structure to, for example, provide a routing for signals out of the chip stack, and is motivated to make the diameter of the first through-via less than that of the first because, for example “. Because the first conductive via 315 has a relatively small width, the first dummy chip 310 may decrease in parasitic capacitance and the semiconductor package 10 may increase in performance” (You, paragraph 0036).
Regarding claim 15, You further teaches, in FIG. 1, “molding layer” 500 and “underfill layer” 530, which constitute an encapsulant encapsulating the second chip. “Connection terminal” 150 is disposed to go through the encapsulation layer (through via) and electrically connects to the first semiconductor chip via through vias 215, 225, and 215, and the rewiring structure via substrate pads 115 (and therefore is configured to supply power to the first semiconductor chip).
It would have been obvious to one having ordinary skill in the art to modify the package taught by Hong such that the package comprises a third through-via extending into the encapsulant to electrically connect the first semiconductor chip and the rewiring structure, and configured to supply power to the first semiconductor chip, as taught by You. One having ordinary skill in the art is motivated to do so in order to, for example, ensure power can be supplied to the first semiconductor chip.
Regarding claim 16, You further teaches, in FIG. , “substrate pads” (connection structure) 115 disposed on the rewiring structure.
It would have been obvious to one having ordinary skill in the art to further modify the package structure taught by Hong such that the package structure comprises a connection structure disposed on the rewiring structure, as taught by You. One having ordinary skill in the art is motivated to do so in order to, for example, ensure stable electrical connection between the rewiring structure and the first semiconductor chip.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20190157244 A1) in view of You (US 20210167040 A1) in further view of Wu (WO 2023010259 A1).
Regarding claim 13, as explained above, Hong and You teach the limitations of claim 12. They do not explicitly teach the diameters of through-vias.
Wu teaches, in FIG. 22, a semiconductor package with a first chip 200 and a second chip 300 disposed on the backside of the first chip. Wu further teaches, in FIG. 7, a “TSV” 2003 on the lower region of a packaging structure and in which “. . . diameter R of the first TSV 2003 may be 0.5 μm . . .”
It would have been obvious to one having ordinary skill in the art to construct the package structure taught by Hong and You such that the diameter of the first (smaller) through via is 0.1-1 μm as taught by Wu. One having ordinary skill in the art is motivated to do so in order to, for example, make the package structure smaller, improving commercial viability. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20190157244 A1) in view of You (US 20210167040 A1) in further view of Farooq (US 20220359482 A1).
Regarding claim 14, as explained above, Hong and You teach the limitations of claim 12. They do not explicitly teach diameters of through-vias.
Farooq teaches, in FIG. 1, a semiconductor package with a first “translator chip” (semiconductor chip) 10 and a second “logic chip” 5, disposed on the backside of the first chip. Additionally, the first chip has “TSVs” 13 and the second chip has “TSVs” 6, in which the second TSVs have a lesser diameter than the first TSVs. Additionally, Farooq teaches, in paragraph 0033 “TSVs 6 can be 50 um by 50 um.”
It would have been obvious to one of ordinary skill in the art to further modify the device taught by Hong such that the diameter of the second through-via is 2 to 50 µm, as taught by Farooq. One having ordinary skill in the art is motivated to do so in order to, for example, reduce resistance in the chip. The examiner notes that while the TSVs taught by Farooq do not necessarily provide power to the chip, one having ordinary skill in the art can easily utilize such a structure for power transfer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:Bitz (US 9960150 B2) – a package structure with multiple stacked chips, TSVs, contact structures, and an encapsulant.
Lee (US 20220359439 A1) – package structure with multiple stacked ships, TSVs, and bonding pads in contact with each other, as well as an encapsulant and TSVs penetrating the encapsulant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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