Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification Objection
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2 and 9-11 rejected under 35 U.S.C. 103 as being unpatentable over Sakuma (U.S. Patent Pub. No. 2020/0303418), in view of Ito (U.S. Patent Pub. No. 2003/0141528).
Regarding Claim 1
FIG. 5 (annotated below) of Sakuma discloses a semiconductor memory device comprising: a first gate electrode layer (G1) extending in a first direction (Z); a second gate electrode layer G2) extending in the first direction and disposed in a second direction (Y) intersecting (crossing) the first direction with respect to the first gate electrode layer; a third gate electrode layer (G3) extending in the first direction and disposed in a third direction (X) intersecting the first direction and the second direction with respect to the first gate electrode layer; a fourth gate electrode layer (G4) extending in the first direction, disposed in the second direction with respect to the third gate electrode layer, and disposed in the third direction with respect to the second gate electrode layer; a first semiconductor layer (S1) extending in the second direction and disposed between the first gate electrode layer and the third gate electrode layer, and between the second gate electrode layer and the fourth gate electrode layer; a first charge storage layer (CS1) disposed between the first gate electrode layer and the first semiconductor layer; a second charge storage layer (CS2) disposed between the second gate electrode layer and the first semiconductor layer; a third charge storage layer (CS3) disposed between the third gate electrode layer and the first semiconductor layer; a fourth charge storage layer (CS4) disposed between the fourth gate electrode layer and the first semiconductor layer.
Sakuma is silent with respect to “a first wiring layer extending in the third direction and being electrically connected to the first gate electrode layer; a second wiring layer extending in the third direction, disposed in the second direction with respect to the first wiring layer, and being electrically connected to the second gate electrode layer; a third wiring layer extending in the third direction and being electrically connected to the third gate electrode layer; and a fourth wiring layer extending in the third direction, disposed in the second direction with respect to the third wiring layer, and being electrically connected to the fourth gate electrode layer, wherein the first wiring layer is disposed between the third wiring layer and the fourth wiring layer, and the second wiring layer disposed between the first wiring layer and the fourth wiring layer”.
FIG. 2 of Ito discloses a similar semiconductor memory device, comprising ; a first wiring layer (WL1) extending in the third direction and being electrically connected to the first gate electrode layer; a second wiring layer (WL2) extending in the third direction, disposed in the second direction with respect to the first wiring layer, and being electrically connected to the second gate electrode layer; a third wiring layer (WL3) extending in the third direction and being electrically connected to the third gate electrode layer; and a fourth wiring layer (WL4) extending in the third direction, disposed in the second direction with respect to the third wiring layer, and being electrically connected to the fourth gate electrode layer, wherein the first wiring layer is disposed between the third wiring layer and the fourth wiring layer, and the second wiring layer disposed between the first wiring layer and the fourth wiring layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sakuma, as taught by Ito. The ordinary artisan would have been motivated to modify Sakuma in the above manner for purpose of improving integration ([0002] of Ito).
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Regarding Claim 2
FIG. 3 of Sakuma discloses a substrate (S), wherein the second direction (Y) is a direction along a surface of the substrate.
Regarding Claim 9
FIG. 5 (annotated above) of Sakuma discloses a second semiconductor layer (S2) disposed in the third direction with respect to the first semiconductor layer, and extending in the second direction, wherein the first gate electrode layer and the second gate electrode layer are disposed between the first semiconductor layer and the second semiconductor layer.
Regarding Claim 10
FIG. 5 of Sakuma discloses a third semiconductor layer (110 for ML1) disposed in the first direction with respect to the first semiconductor layer, extending in the second direction, disposed between the first gate electrode layer and the third gate electrode layer, and disposed between the second gate electrode layer and the fourth gate electrode layer.
Regarding Claim 11
FIG. 5 of Sakuma discloses the gate electrodes include tungsten [0079].
Claims 1, 3, 7-9 and 11-13 rejected under 35 U.S.C. 103 as being unpatentable over Sohn (U.S. Patent Pub. No. 2017/0338243), in view of Miyamoto (U.S. Patent Pub. No. 2005/0052914).
Regarding Claim 1
FIG. 2 of Sohn discloses a semiconductor memory device comprising: a first gate electrode layer (50a for M1_A) extending in a first direction (x); a second gate electrode layer (50a for M2_A) extending in the first direction and disposed in a second direction (z) intersecting the first direction with respect to the first gate electrode layer; a third gate electrode layer (50b for M1_B) extending in the first direction and disposed in a third direction (y) intersecting the first direction and the second direction with respect to the first gate electrode layer; a fourth gate electrode layer (50b for M2_B) extending in the first direction, disposed in the second direction with respect to the third gate electrode layer, and disposed in the third direction with respect to the second gate electrode layer; a first semiconductor layer (20) extending in the second direction and disposed between the first gate electrode layer and the third gate electrode layer, and between the second gate electrode layer and the fourth gate electrode layer; a first charge storage layer (40 for M1_A) disposed between the first gate electrode layer and the first semiconductor layer; a second charge storage layer (40 for M1_B) disposed between the second gate electrode layer and the first semiconductor layer; a third charge storage layer (40 for M2_A) disposed between the third gate electrode layer and the first semiconductor layer; a fourth charge storage layer (40 for M2_B) disposed between the fourth gate electrode layer and the first semiconductor layer.
Sohn is silent with respect to “a first wiring layer extending in the third direction and being electrically connected to the first gate electrode layer; a second wiring layer extending in the third direction, disposed in the second direction with respect to the first wiring layer, and being electrically connected to the second gate electrode layer; a third wiring layer extending in the third direction and being electrically connected to the third gate electrode layer; and a fourth wiring layer extending in the third direction, disposed in the second direction with respect to the third wiring layer, and being electrically connected to the fourth gate electrode layer, wherein the first wiring layer is disposed between the third wiring layer and the fourth wiring layer, and the second wiring layer disposed between the first wiring layer and the fourth wiring layer”.
FIG. 1 (annotated below) of Miyamoto discloses a similar semiconductor memory device, comprising ; a first wiring layer (W1) extending in the third direction and being electrically connected to the first gate electrode layer (G1); a second wiring layer (W2) extending in the third direction, disposed in the second direction with respect to the first wiring layer, and being electrically connected to the second gate electrode layer (G2); a third wiring layer (W3) extending in the third direction and being electrically connected to the third gate electrode layer (G3); and a fourth wiring layer (W4) extending in the third direction, disposed in the second direction with respect to the third wiring layer, and being electrically connected to the fourth gate electrode layer (G4), wherein the first wiring layer is disposed between the third wiring layer and the fourth wiring layer, and the second wiring layer disposed between the first wiring layer and the fourth wiring layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sohn, as taught by Miyamoto. The ordinary artisan would have been motivated to modify Sohn in the above manner for purpose of allowing miniaturization ([0012] of Miyamoto).
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Regarding Claim 3
FIG. 2 of Sohn discloses the first gate electrode layer (50) has a major axis and a minor axis shorter than the major axis in a cross section perpendicular to the first direction.
Regarding Claim 7
FIG. 1 of Miyamoto discloses a first connection portion provided between the first gate electrode layer and the first wiring layer, and connecting the first gate electrode layer and the first wiring layer; a second connection portion disposed between the second gate electrode layer and the second wiring layer, and connecting the second gate electrode layer and the second wiring layer; a third connection portion disposed between the third gate electrode layer and the third wiring layer, and connecting the third gate electrode layer and the third wiring layer; and a fourth connection portion disposed between the fourth gate electrode layer and the fourth wiring layer, and connecting the fourth gate electrode layer and the fourth wiring layer, wherein a direction in which the first connection portion and the second connection portion are connected intersects the second direction, and a direction in which the third connection portion and the fourth connection portion are connected intersects the second direction.
Regarding Claim 8
FIG. 1 of Miyamoto discloses the direction in which the first connection portion and the second connection portion are connected intersects the direction in which the third connection portion and the fourth connection portion are connected.
Regarding Claim 9
FIG. 2 of Sohn discloses a second semiconductor layer (20) disposed in the third direction with respect to the first semiconductor layer, and extending in the second direction, wherein the first gate electrode layer and the second gate electrode layer are disposed between the first semiconductor layer and the second semiconductor layer.
Regarding Claim 11
FIG. 2 of Sohn discloses the gate electrodes include tungsten [0080].
Regarding Claim 12
FIG. 2 of Sohn discloses the charge storage layers (40) each include a tunnel insulating film (41), a charge storage area (42), and a block insulating film (43) [0061].
Regarding Claim 13
FIG. 2 of Sohn discloses the first semiconductor layer includes polycrystalline silicon [0057].
Claims 4-6 rejected under 35 U.S.C. 103 as being unpatentable over Sohn and Miyamoto, in view of Dunkel (U.S. Patent Pub. No. 2020/0176456).
Regarding Claim 4
Sohn as modified by Miyamoto discloses Claim 3.
Sohn as modified by Miyamoto is silent with respect to “the first gate electrode layer is elliptical in the cross section perpendicular to the first direction”.
FIG. 2 of Dunkel discloses a similar semiconductor memory device, wherein the first gate electrode layer (12a) is elliptical in the cross section perpendicular to the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sohn, as taught by Dunkel. The ordinary artisan would have been motivated to modify Sohn in the above manner for purpose of allowing more robust or denser memory arrays ([0012] of Dunkel).
Regarding Claim 5
FIG. 2 of Dunkel discloses in the cross section perpendicular to the first direction, an angle between a direction of the major axis and the second direction is less than 90 degrees [0019].
Regarding Claim 6
FIG. 2 of Dunkel discloses in the cross section perpendicular to the first direction, an angle between a direction of the major axis and the second direction is 45 degrees or more and 75 degrees or less [0019].
Claims 14 and 15 rejected under 35 U.S.C. 103 as being unpatentable over Sakuma and Ito, in view of Wu (U.S. Patent Pub. No. 2021/0399052).
Regarding Claim 14
Sakuma as modified by Ito discloses Claim 1.
Sakuma as modified by Ito is silent with respect to “the wiring layers include at least one of tungsten, aluminum or copper”.
FIG. 13 of Ito discloses a similar semiconductor memory device, the wiring layers (WL) include at least one of tungsten, aluminum or copper [0047].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sakuma, as taught by Ito. The ordinary artisan would have been motivated to modify Sakuma in the above manner for purpose of excellent conductivity.
Regarding Claim 15
Wu discloses the substrate is formed of single crystal silicon [0016].
Pertinent Art
U.S. 2011/0101434, 2017/0125433 2022/0406378, 9,589,982, CN 104157654.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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