Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 7, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein an upper surface of the second residue is at a lower level than an upper surface of the first residue”, as recited in claim 3.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected on the basis that it contains an improper Markush grouping of alternatives. See In re Harnisch, 631 F.2d 716, 721-22 (CCPA 1980) and Ex parte Hozumi, 3 USPQ2d 1059, 1060 (Bd. Pat. App. & Int. 1984). A Markush grouping is proper if the alternatives defined by the Markush group (i.e., alternatives from which a selection is to be made in the context of a combination or process, or alternative chemical compounds as a whole) share a “single structural similarity” and a common use. A Markush grouping meets these requirements in two situations. First, a Markush grouping is proper if the alternatives are all members of the same recognized physical or chemical class or the same art-recognized class, and are disclosed in the specification or known in the art to be functionally equivalent and have a common use. Second, where a Markush grouping describes alternative chemical compounds, whether by words or chemical formulas, and the alternatives do not belong to a recognized class as set forth above, the members of the Markush grouping may be considered to share a “single structural similarity” and common use where the alternatives share both a substantial structural feature and a common use that flows from the substantial structural feature. See MPEP § 2117.
The Markush grouping of “and/or” in claim 19, line 5 is improper because the alternatives defined by the Markush grouping do not share both a single structural similarity and a common use.
To overcome this rejection, Applicant may set forth each alternative (or grouping of patentably indistinct alternatives) within an improper Markush grouping in a series of independent or dependent claims and/or present convincing arguments that the group members recited in the alternative within a single claim in fact share a single structural similarity as well as a common use.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2015/0035023 A1, hereinafter refer to Kim) in view of SUH et al. (U.S. 2014/0374827 A1, hereinafter refer to SUH).
Regarding Claim 1: Kim discloses a method of forming a semiconductor device (see Kim, Figs.20, 22B, 29-37 as shown below and ¶ [0003]), comprising:
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forming an active fin (F11/F12 or F21/F22), wherein the active fin (F11/F12 or F21/F22) comprises a first fin area (198) and a second fin area (199) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming an isolation layer (110) on a side surface of a lower portion of the active fin (F11/F12 or F21/F22) (see Kim, Fig.29 as shown above);
forming a sacrificial gate (141/143) on the first fin area (198) of the active fin (F11/F12 or F21/F22) and the isolation layer (110) (see Kim, Figs.20, 22B, and 29 as shown above);
forming a recessed second fin area (199) by etching the second fin area (199), after forming the sacrificial gate (141/143) (see Kim, Figs.20, 22B, and 29-30 as shown above and ¶ [0176]- ¶ [0179]);
forming an asymmetric source/drain (123/124/129) on the recessed second fin area (199) (see Kim, Fig.32 as shown above);
forming an interlayer insulating layer (171) on the asymmetric source/drain (123/124/129) and the isolation layer (110) (see Kim, Fig.35 as shown above);
forming a gate trench (133) by removing the sacrificial gate (141/143), after forming the interlayer insulating layer (171) (see Kim, Fig.29 as shown above and ¶ [0195]- ¶ [0197]);
forming a gate structure (147) in the gate trench (133) (see Kim, Fig.29 as shown above),
wherein the asymmetric source/drain (123/124/129) comprises a first crystal growth portion (123/124) and a second crystal growth portion (129) that shares a plane with the first crystal growth portion (123/124) and that has a lower surface at a lower level than a lower surface of the first crystal growth portion (123/124) (see Kim, Figs.33-34 as shown above).
Kim is silent upon explicitly disclosing wherein forming fin spacers on side surfaces of the second fin area,
forming a first residue on a first side surface of the recessed second fin area and a second residue on a second side surface of the recessed second fin area by etching the fin spacers, before forming the asymmetric source/drain.
For support see SUH, which teaches wherein forming fin spacers (1511) on side surfaces of the second fin area (120) (see SUH, Figs.15-16 as shown below and ¶ [0007]),
forming a first residue (125) on a first side surface of the recessed second fin area (120) and a second residue (125) on a second side surface of the recessed second fin area (120) by etching the fin spacers (1511), before forming the asymmetric source/drain (161) (see SUH, Figs.15-17 as shown below and ¶ [0007]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and SUH to enable forming fin spacers on side surfaces of the second fin area, and forming a first residue on a first side surface of the recessed second fin area and a second residue on a second side surface of the recessed second fin area by etching the fin spacers, before forming the asymmetric source/drain as taught by SUH as taught by SUH in order to improve a characteristic of the device.
Regarding Claim 2: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 1 as above. The combination of Kim and SUH further teaches wherein forming an insulating spacer layer (1511) on the sacrificial gate (142), the second fin area (120) and the isolation layer (110), before forming the recessed second fin area (120) (see SUH, Fig.15 as shown above); and
forming a gate spacer (141) on a side surface of the sacrificial gate (142) (see SUH, Fig.16 as shown above),
wherein the first side surface of the recessed second fin area (120) is opposite to the second side surface of the recessed second fin area (120) (see SUH, Fig.16 as shown above and Figs.19-20),
wherein the first residue (125) and the second residue (125) comprise a same material (see SUH, Fig.16 as shown above).
The combination of Kim and SUH is silent upon explicitly disclosing wherein the first residue is between the first crystal growth portion and the isolation layer,
wherein the second residue is between the second crystal growth portion and the isolation layer.
However, practicing the combination of Kim and SUH to modify Kim’s structure to include a first residue on a first side surface of the recessed second fin area and a second residue on a second side surface of the recessed second fin area by etching the fin spacers, before forming the asymmetric source/drain according to the teachings of SUH necessary results the claimed limitation of “the first residue is between the first crystal growth portion and the isolation layer,
wherein the second residue is between the second crystal growth portion and the isolation layer” as now specified in claim 2.
Regarding Claim 17: Kim discloses a method of forming a semiconductor device (see Kim, Figs.20, 22B, 29-37 as shown above and ¶ [0003]), comprising:
forming an active fin (F11/F12 or F21/F22) protruding from a substrate (100), wherein the active fin (F11/F12 or F21/F22) comprises a first fin area (198) and a second fin area (199) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming an isolation layer (110) on a side surface of a lower portion of the active fin (F11/F12 or F21/F22) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming a sacrificial gate (141/143) on the first fin area (198) of the active fin and the isolation layer (110) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming a recessed second fin area (199) by etching the second fin area (199), after forming the sacrificial gate (141/143) (see Kim, Figs.20, 22B, and 29-30 as shown above and ¶ [0176]- ¶ [0179]);
forming a diamond-shaped source/drain (123/124/129) on the recessed second fin area (199) (see Kim, Fig.34 as shown above, ¶ [0013], and ¶ [0041]);
forming an interlayer insulating layer (171) on the diamond-shaped source/drain (123/124/129) and the isolation layer (110) (see Kim, Fig.35 as shown above);
forming a gate trench (133) by removing the sacrificial gate (141/143), after forming the interlayer insulating layer (171) (see Kim, Figs.34-35 as shown above);
forming a gate structure (147) in the gate trench (133) (see Kim, Figs.35-36 as shown above),
wherein the diamond-shaped source/drain (123/124/129) comprises a first crystal growth portion (123/124) and a second crystal growth portion (129), and wherein the second crystal growth portion (129) comprises a lower surface that is at a lower level than a lower surface of the first crystal growth portion (123/124) (see Kim, Fig.34 as shown above).
Kim is silent upon explicitly disclosing wherein forming fin spacers on side surfaces of the second fin area,
forming a first residue on a first side surface of the recessed second fin area and a second residue on a second side surface of the recessed second fin area by etching the fin spacers, before forming the diamond-shaped source/drain.
For support see SUH, which teaches wherein forming fin spacers (1511) on side surfaces of the second fin area (120) (see SUH, Figs.15-16 as shown above and ¶ [0007]),
forming a first residue (125) on a first side surface of the recessed second fin area (120) and a second residue (125) on a second side surface of the recessed second fin area (120) by etching the fin spacers (1511), before forming the diamond-shaped source/drain (161) (see SUH, Figs.15-17 as shown above and ¶ [0007]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and SUH to enable forming fin spacers on side surfaces of the second fin area, and forming a first residue on a first side surface of the recessed second fin area and a second residue on a second side surface of the recessed second fin area by etching the fin spacers, before forming the diamond-shaped source/drain as taught by SUH as taught by SUH in order to improve a characteristic of the device.
Regarding Claim 18: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 17 as above. The combination of Kim and SUH further teaches wherein forming an insulating spacer layer (1511) on the sacrificial gate (142), the second fin area (120) and the isolation layer (110), before forming the recessed second fin area (see SUH, Fig.15 as shown above);
forming a gate spacer (141) on a side surface of the sacrificial gate (142) (see SUH, Fig.16 as shown above),
wherein the first side surface of the recessed second fin area is opposite to the second side surface of the recessed second fin area (see SUH, Fig.16 as shown above and Figs.19-20).
Claim(s) 7-8, 10-14, 16, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2015/0035023 A1, hereinafter refer to Kim) in view of Lim et al. (U.S. 2016/0268257 A1, hereinafter refer to Lim).
Regarding Claim 7: Kim discloses a method of forming a semiconductor device (see Kim, Figs.20, 22B, 29-37 as shown above and ¶ [0003]), comprising:
forming active fins (F11/F12 or F21/F22), wherein each of the active fins (F11/F12 or F21/F22) comprises a first fin area (198) and a second fin area (199) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming an isolation layer (110) on side surfaces of lower portions of the active fins (F11/F12 or F21/F22) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming a sacrificial gate (141/143) on the first fin areas (198) of the active fins (F11/F12 or F21/F22) and the isolation layer (110) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming recessed second fin areas (199) by etching the second fin areas (199) of the active fins, after forming the sacrificial gate (141/143) (see Kim, Figs.20, 22B, and 29-30 as shown above and ¶ [0176]- ¶ [0179]);
forming a source/drain (123/124/125/127/129) on the recessed second fin areas (199) (see Kim, Fig.32 as shown above);
forming an interlayer insulating layer (171) on the source/drain (123/124/125/127/129) and the isolation layer (123/124/125/127/129) (see Kim, Figs.34-35 as shown above);
forming a gate trench (133) by removing the sacrificial gate (141/143), after forming the interlayer insulating layer (171) (see Kim, Figs.34-35 as shown above); and
forming a gate structure (147) in the gate trench (133) (see Kim, Figs.35-36 as shown above),
wherein the source/drain contacts (187) at least two of the active fins (F11/F12 or F21/F22) at a same time and has a merged double-diamond shape (see Kim, Fig.36-37 as shown above),
wherein the source/drain (123/124/125/127/129) comprises first crystal growth portions (123/124) that contact upper surfaces of the recessed second fin areas (199) of the at least two of the active fins (F11/F12 or F21/F22), second crystal growth portions (129) that share at least one plane with the first crystal growth portions (123/124) and that contact side surfaces of the recessed second fin areas (199) of the at least two of the active fins (F11/F12 or F21/F22), and a third crystal growth portion (125/127) formed to merge adjacent edges of the first crystal growth portions (123/124) (see Kim, Fig.34 as shown above),
wherein the at least two of the active fins (F11/F12 or F21/F22) comprise a first active fin (F11 or F21) and a second active fin (F12 or F22) adjacent to the first active fin (F11 or F21) in a first direction (see Kim, Figs.20, 22B, 29-37 as shown above),
wherein the first active fin (F11 or F21) has a first side surface facing the second active fin (F12 or F22) and a second side surface opposite to the first side surface in the first direction (see Kim, Figs.20, 22B, 29-37 as shown above),
wherein the isolation layer(110) comprises:
a first isolation portion (110) between the first active fin (F11 or F21) and the second active fin (F12 or F22), and vertically overlapping the source/drain (123/124/125/127/129) (see Kim, Figs.29-37 as shown above); and
a second isolation portion (110) disposed on the second side surface of the first active fin (F11 or F21) and vertically overlapping the source/drain (123/124/125/127/129) (see Kim, Figs.29-37 as shown above).
Kim is silent upon explicitly disclosing wherein a first lower end of the source/drain vertically overlapping the first isolation portion is at a higher level than a second lower end of the source/drain vertically overlapping the second isolation portion.
For support see Lim, which teaches wherein a first lower end of the source/drain (1820) vertically overlapping the first isolation portion (710/1210) is at a higher level than a second lower end of the source/drain (1820) vertically overlapping the second isolation portion (710) (see Lim, Fig.19 as shown below and ¶ [0042]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Lim to enable the first lower end of the source/drain vertically overlapping the first isolation portion to be at a higher level than a second lower end of the source/drain vertically overlapping the second isolation portion as taught by Lim in order to increase the current drive of a finFET by controlling the deposition of an EPI layer.
Regarding Claim 8: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 7 as above. The combination of Kim and Lim further teaches wherein the second crystal growth portions (129) contact opposite side surfaces of adjacent the recessed second fin areas (199) (see Kim, Fig.34 as shown above).
Regarding Claim 10: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 7 as above. The combination of Kim and Lim further teaches wherein an upper surface of the first isolation portion (710/1210) is at a lower level than the upper surfaces of the recessed second fin areas (see Lim, Fig.19 as shown above).
Regarding Claim 11: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 10 as above. The combination of Kim and Lim further teaches wherein the upper surface of the first isolation portion (110) is spaced apart from the third crystal growth portion (125/127) (see Kim, Fig.34 as shown above).
Regarding Claim 12: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 7 as above. The combination of Kim and Lim further teaches wherein lower surfaces of the first crystal growth portions (123/124) are at a higher level than lower surfaces of the second crystal growth portions (129), and at a lower level than a lower surface of the third crystal growth portion (125/127) (see Kim, Fig.34 as shown above).
Regarding Claim 13: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 7 as above. The combination of Kim and Lim further teaches wherein lower surfaces of the first crystal growth portions (123/124) contact an upper surface of the isolation layer (110) (see Kim, Fig.32 as shown above).
Regarding Claim 14: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 13 as above. The combination of Kim and Lim further teaches wherein lower surfaces of the second crystal growth portions (129) contact an upper surface of the isolation layer (110) (see Kim, Fig.34 as shown above).
Regarding Claim 16: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 7 as above. The combination of Kim and Lim further teaches wherein forming a contact electrode (181) that extends into the interlayer insulating layer (171), wherein the contact electrode (181) contacts the third crystal growth portion (125/127) and at least one of the first crystal growth portions (123/124) (see Kim, Fig.37 as shown above and Fig.16).
Regarding Claim 22: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 7 as above. The combination of Kim and Lim further teaches wherein an upper end of the second isolation portion (710/1210) is at a higher level than a center of an upper surface of the first isolation portion (710) (see Lim, Fig.19 as shown above).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2015/0035023 A1, hereinafter refer to Kim) and SUH et al. (U.S. 2014/0374827 A1, hereinafter refer to SUH) as applied to claim 17 above, and further in view of Murthy et al. (U.S. 2011/0147828 A1, hereinafter refer to Murthy).
Regarding Claim 20: Kim as modified teaches a method of forming a semiconductor device as applied to claim 17 above. The combination of Kim and SUH is silent upon explicitly disclosing wherein dopant concentration of the diamond-shaped source/drain gradually increases towards an upper end of the diamond-shaped source/drain.
For support see Murthy, which teaches wherein dopant concentration of the diamond-shaped source/drain (531/541) gradually increases towards an upper end of the diamond-shaped source/drain (531/541) (see Murthy, Figs.2 and 4 as shown below, ¶ [0018], ¶ [0026]- ¶ [0027], ¶ [0057], and ¶ [0060]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim, SUH, and Murthy to enable dopant concentration of the diamond-shaped source/drain to gradually increase towards an upper end of the diamond-shaped source/drain as taught by Murthy in order to increase electron mobility at channel region, reduce short channel effects, and reduce parasitic resistance.
Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2015/0035023 A1, hereinafter refer to Kim) and Lim et al. (U.S. 2016/0268257 A1, hereinafter refer to Lim) as applied to claim 7 above, and further in view of SUH et al. (U.S. 2014/0374827 A1, hereinafter refer to SUH).
Regarding Claim 21: Kim as modified teaches a method of forming a semiconductor device as applied to claim 7 above. The combination of Kim and Lim is silent upon explicitly disclosing wherein forming a gate spacer on a side surface of the sacrificial gate, and
forming fin spacers on side surfaces of the second fin areas; and
forming a first residue on a first side surface of at least one of the recessed second fin areas and a second residue on a second side surface of the at least one of the recessed second fin areas by etching the fin spacers, before forming the source/drain,
wherein the first side surface is opposite to the second side surface.
For support see SUH, which teaches wherein forming a gate spacer (151) on a side surface of the sacrificial gate (142) (see SUH, Fig.16 as shown above and ¶ [0007]), and
forming fin spacers (1511) on side surfaces of the second fin areas (120) (see SUH, Fig.15 as shown above); and
forming a first residue (125) on a first side surface of at least one of the recessed second fin areas and a second residue (125) on a second side surface of the at least one of the recessed second fin areas by etching the fin spacers (1511), before forming the source/drain (161) (see SUH, Figs.16-17 as shown above and Figs.19-20),
wherein the first side surface is opposite to the second side surface (see SUH, Fig.16 as shown above).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim, Lim, and SUH to enable forming a gate spacer on a side surface of the sacrificial gate, and forming fin spacers on side surfaces of the second fin areas; and forming a first residue on a first side surface of at least one of the recessed second fin areas and a second residue on a second side surface of the at least one of the recessed second fin areas by etching the fin spacers, before forming the source/drain, wherein the first side surface is opposite to the second side surface as taught by SUH as taught by SUH in order to improve a characteristic of the device.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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