DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 2-6 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein forming an insulating spacer layer on the sacrificial gate, the second fin area and the isolation layer, before forming the recessed second fin area;
forming a gate spacer on a side surface of the sacrificial gate, and
forming fin spacers on side surfaces of the second fin area; and forming a first residue on a first side surface of the recessed second fin area and a second residue on a second side surface of the recessed second fin area by etching the fin spacers, before forming the asymmetric source/drain,
wherein the first side surface of the recessed second fin area is opposite to the second side surface of the recessed second fin area,
wherein the first residue is between the first crystal growth portion and the isolation layer,
wherein the second residue is between the second crystal growth portion and the isolation layer, and wherein the first residue and the second residue comprise a same material”, as recited in claim 2.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “forming an insulating spacer layer on the sacrificial gate, the second fin area and the isolation layer, before forming the recessed second fin area;
forming a gate spacer on a side surface of the sacrificial gate, and forming fin spacers on side surfaces of the second fin area; and
forming a first residue on a first side surface of the recessed second fin area and a second residue on a second side surface of the recessed second fin area by etching the fin spacers, before forming the diamond-shaped source/drain,
wherein the first side surface of the recessed second fin area is opposite to the second side surface of the recessed second fin area”, as recited in claim 18.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7-9, and 12-17 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim et al. (U.S. 2015/0035023 A1, hereinafter refer to Kim)
Regarding Claim 1: Kim discloses a method of forming a semiconductor device (see Kim, Figs.20, 22B, 29-37 as shown below and ¶ [0003]), comprising:
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forming an active fin (F11/F12 or F21/F22), wherein the active fin (F11/F12 or F21/F22) comprises a first fin area (198) and a second fin area (199) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming an isolation layer (110) on a side surface of a lower portion of the active fin (F11/F12 or F21/F22) (see Kim, Fig.29 as shown above);
forming a sacrificial gate (141/143) on the first fin area (198) of the active fin (F11/F12 or F21/F22) and the isolation layer (110) (see Kim, Figs.20, 22B, and 29 as shown above);
forming a recessed second fin area (199) by etching the second fin area (199), after forming the sacrificial gate (141/143) (see Kim, Figs.20, 22B, and 29-30 as shown above and ¶ [0176]- ¶ [0179]);
forming an asymmetric source/drain (123/124/129) on the recessed second fin area (199) (see Kim, Fig.32 as shown above);
forming an interlayer insulating layer (171) on the asymmetric source/drain (123/124/129) and the isolation layer (110) (see Kim, Fig.35 as shown above);
forming a gate trench (133) by removing the sacrificial gate (141/143), after forming the interlayer insulating layer (171) (see Kim, Fig.29 as shown above and ¶ [0195]- ¶ [0197]); and
forming a gate structure (147) in the gate trench (133) (see Kim, Fig.29 as shown above),
wherein the asymmetric source/drain (123/124/129) comprises a first crystal growth portion (123/124) and a second crystal growth portion (129) that shares a plane with the first crystal growth portion (123/124) and that has a lower surface at a lower level than a lower surface of the first crystal growth portion (123/124) (see Kim, Figs.33-34 as shown above).
Regarding Claim 7: Kim discloses a method of forming a semiconductor device (see Kim, Figs.20, 22B, 29-37 as shown above and ¶ [0003]), comprising:
forming active fins (F11/F12 or F21/F22), wherein each of the active fins (F11/F12 or F21/F22) comprises a first fin area (198) and a second fin area (199) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming an isolation layer (110) on side surfaces of lower portions of the active fins (F11/F12 or F21/F22) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming a sacrificial gate (141/143) on the first fin areas (198) of the active fins (F11/F12 or F21/F22) and the isolation layer (110) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming recessed second fin areas (199) by etching the second fin areas (199), after forming the sacrificial gate (141/143) (see Kim, Figs.20, 22B, and 29-30 as shown above and ¶ [0176]- ¶ [0179]);
forming a source/drain (123/124/125/127/129) on the recessed second fin areas (199) (see Kim, Fig.32 as shown above);
forming an interlayer insulating layer (171) on the source/drain (123/124/125/127/129) and the isolation layer (123/124/125/127/129) (see Kim, Figs.34-35 as shown above);
forming a gate trench (133) by removing the sacrificial gate (141/143), after forming the interlayer insulating layer (171) (see Kim, Figs.34-35 as shown above); and
forming a gate structure (147) in the gate trench (133) (see Kim, Figs.35-36 as shown above),
wherein the source/drain contacts (187) at least two of the active fins (F11/F12 or F21/F22) at a same time and has a merged double-diamond shape (see Kim, Fig.36-37 as shown above),
wherein the source/drain (123/124/125/127/129) comprises first crystal growth portions (123/124) that contact upper surfaces of the at least two of the recessed second fin areas (199), second crystal growth portions (129) that share at least one plane with the first crystal growth portions (123/124) and that contact side surfaces of the at least two of the recessed second fin areas (199), and a third crystal growth portion (125/127) formed to merge adjacent edges of the first crystal growth portions (123/124) (see Kim, Fig.34 as shown above).
Regarding Claim 8: Kim discloses a method of forming a semiconductor device as set forth in claim 7 as above. Kim further teaches wherein the second crystal growth portions (129) contact opposite side surfaces of adjacent the recessed second fin areas (199) (see Kim, Fig.34 as shown above).
Regarding Claim 9: Kim discloses a method of forming a semiconductor device as set forth in claim 7 as above. Kim further teaches wherein the isolation layer (110) comprises an intermediate isolation portion between the at least two of the active fins, and wherein the third crystal growth portion (125/127) is vertically aligned with the intermediate isolation portion (see Kim, Fig.34 as shown above).
Regarding Claim 12: Kim discloses a method of forming a semiconductor device as set forth in claim 7 as above. Kim further teaches wherein lower surfaces of the first crystal growth portions (123/124) are at a higher level than lower surfaces of the second crystal growth portions (129), and at a lower level than a lower surface of the third crystal growth portion (125/127) (see Kim, Fig.34 as shown above).
Regarding Claim 13: Kim discloses a method of forming a semiconductor device as set forth in claim 7 as above. Kim further teaches wherein lower surfaces of the first crystal growth portions (123/124) contact an upper surface of the isolation layer (110) (see Kim, Fig.32 as shown above).
Regarding Claim 14: Kim discloses a method of forming a semiconductor device as set forth in claim 13 as above. Kim further teaches wherein lower surfaces of the second crystal growth portions (129) contact an upper surface of the isolation layer (110) (see Kim, Fig.34 as shown above).
Regarding Claim 15: Kim discloses a method of forming a semiconductor device as set forth in claim 7 as above. Kim further teaches wherein the at least two of the active fins (F11/F12) comprises a first active fin (F12) and a second active fin (F11) adjacent to the first active fin (F12) in a first direction (see Kim, Fig.12 as shown below),
wherein the isolation layer (110) comprises a first isolation portion (110) and a second isolation portion (110) (see Kim, Fig.12 as shown below),
wherein the first isolation portion (110) is between the first active fin (F12) and the second active fin (F11) (see Kim, Fig.12 as shown below),
wherein the first active fin (F12) is between the first isolation portion (110) and the second isolation portion (110) (see Kim, Fig.12 as shown below), and
wherein a width (W2) in the first direction of the second isolation portion (110) is greater than a width (W1) in the first direction of the first isolation portion (110) (see Kim, Fig.12 as shown below).
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Regarding Claim 16: Kim discloses a method of forming a semiconductor device as set forth in claim 7 as above. Kim further teaches wherein forming a contact electrode (181) that extends into the interlayer insulating layer (171), wherein the contact electrode (181) contacts the third crystal growth portion (125/127) and at least one of the first crystal growth portions (123/124) (see Kim, Fig.37 as shown above and Fig.16).
Regarding Claim 17: Kim discloses a method of forming a semiconductor device (see Kim, Figs.20, 22B, 29-37 as shown above and ¶ [0003]), comprising:
forming an active fin (F11/F12 or F21/F22) protruding from a substrate (100), wherein the active fin (F11/F12 or F21/F22) comprises a first fin area (198) and a second fin area (199) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming an isolation layer (110) on a side surface of a lower portion of the active fin (F11/F12 or F21/F22) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming a sacrificial gate (141/143) on the first fin area (198) of the active fin and the isolation layer (110) (see Kim, Figs. 20, 22B, and 29 as shown above);
forming a recessed second fin area (199) by etching the second fin area (199), after forming the sacrificial gate (141/143) (see Kim, Figs.20, 22B, and 29-30 as shown above and ¶ [0176]- ¶ [0179]);
forming a diamond-shaped source/drain (123/124/129) on the recessed second fin area (199) (see Kim, Fig.34 as shown above, ¶ [0013], and ¶ [0041]);
forming an interlayer insulating layer (171) on the diamond-shaped source/drain (123/124/129) and the isolation layer (110) (see Kim, Fig.35 as shown above);
forming a gate trench (133) by removing the sacrificial gate (141/143), after forming the interlayer insulating layer (171) (see Kim, Figs.34-35 as shown above); and
forming a gate structure (147) in the gate trench (133) (see Kim, Figs.35-36 as shown above),
wherein the diamond-shaped source/drain (123/124/129) comprises a first crystal growth portion (123/124) and a second crystal growth portion (129), and wherein the second crystal growth portion (129) comprises a lower surface that is at a lower level than a lower surface of the first crystal growth portion (123/124) (see Kim, Fig.34 as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 -11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2015/0035023 A1, hereinafter refer to Kim) as applied to claim 7 above, and further in view of Kim et al. (U.S. 2014/0299934 A1, hereinafter refer to Kim’934).
Regarding Claim 10: Kim discloses a method of forming a semiconductor device as applied to claim 7 above. Kim further teaches wherein the at least two of the active fins (F11/F12 or F21/F22) comprises a first active fin (F11 or F21) and a second active fin (F12 or F22) adjacent to the first active fin (F11 or F21), wherein the isolation layer (110) comprises an intermediate isolation portion between the first active fin (F11 or F21) and the second active fin (F12 or F22) (see Kim, Fig.34 as shown above).
Kim is silent upon explicitly disclosing wherein an upper surface of the intermediate isolation portion is at a lower level than the upper surfaces of the recessed second fin areas.
For support see Kim’934, which teaches an upper surface of the intermediate isolation portion (110) is at a lower level than the upper surfaces of the recessed second fin areas (see Kim’934, Figs.17 and 21 as shown below and ¶ [0005]- ¶ [0006]).
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Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Kim’934 to enable the upper surface of the intermediate isolation portion to be at a lower level than the upper surfaces of the recessed second fin areas according to the teachings of Kim’934 because one of ordinary skill in the art at the time of the invention would have been motivated to look to alternative suitable methods of performing the disclosed isolation layer step of Kim and art recognized suitability for reducing interference between adjacent transistors and/or which can apply strain to a channel region has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 11: Kim as modified teaches a method of forming a semiconductor device as set forth in claim 10 as above. The combination of Kim and Kim’934 further teaches wherein the upper surface of the intermediate isolation portion (110) is spaced apart from the third crystal growth portion (125/127) (see Kim, Fig.34 as shown above).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2015/0035023 A1, hereinafter refer to Kim) as applied to claim 17 above, and further in view of Murthy et al. (U.S. 2011/0147828 A1, hereinafter refer to Murthy).
Regarding Claim 20: Kim discloses a method of forming a semiconductor device as applied to claim 17 above. Kim is silent upon explicitly disclosing wherein dopant concentration of the diamond-shaped source/drain gradually increases towards an upper end of the diamond-shaped source/drain.
For support see Murthy, which teaches wherein dopant concentration of the diamond-shaped source/drain (531/541) gradually increases towards an upper end of the diamond-shaped source/drain (531/541) (see Murthy, Figs.2 and 4 as shown below, ¶ [0018], ¶ [0026]- ¶ [0027], ¶ [0057], and ¶ [0060]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Murthy to enable dopant concentration of the diamond-shaped source/drain to gradually increase towards an upper end of the diamond-shaped source/drain as taught by Murthy in order to increase electron mobility at channel region, reduce short channel effects, and reduce parasitic resistance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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