Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 21, “a first semiconductor die” in line 1 is unclear whether it is referring to the same “first semiconductor die” recited in claim 1, lines 9-10, the method step of this “first semiconductor die”, or to some other “first semiconductor die”. For the sake of compact prosecution, claim 21 is interpreted in the instant Office action as follows: “a first semiconductor die” in line 1 is referring back, and adding further limitation to the same “positioning” step recited in claim 1, and is equivalent to “positioning a first semiconductor die”. This interpretation is to be confirmed by applicant in next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 3-6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu (US 20210118859 A1).
Regarding claim 1, Yu discloses a method of manufacturing a semiconductor device (Fig. 3A), comprising:
individually placing each of a plurality of capacitors (80; [0027]: “includes passive devices…capacitors”. Note: each plurality of the single plurality is placed) on a front side of a semiconductor package substrate (20; [0016]: “includes a semiconductor substrate”. Note: 20 is a component assembled with a collection of other components, thus it is a package substrate) adjacent to a central portion of the front side (See annotated figure for portion designation),
wherein individually placing each of the plurality of capacitors comprises electrically coupling each of the plurality of capacitors to the front side of the semiconductor package substrate (coupled by 88);
at least partially encasing the plurality of capacitors with an encapsulant material (104; as shown in the method step of Fig. 4A):
after at least partially encasing the plurality of capacitors (as shown in the method step of Fig. 5A), positioning a first semiconductor die (40; [0021]: “includes a semiconductor substrate”) on the front side of the semiconductor package substrate within the central portion (indirectly on) such that a lower surface of the first semiconductor die is electrically coupled to the central portion (coupled by 106),
wherein the first semiconductor die and the plurality of capacitors are within a region having a first longitudinal footprint (See annotated Fig. 16 for footprint designation);
attaching a second semiconductor die (402; [0079]: “made of a semiconductor material”) to the plurality of capacitors and the first semiconductor die (indirectly attached),
wherein the second semiconductor die has a second longitudinal footprint (See annotated Fig. 16 for footprint designation) equal to or greater than the first longitudinal footprint (“greater than” because First is fully within Second), and
wherein a lower surface of the second semiconductor die (See annotated Fig. 16 for surface designation. Note: “lower surface” is mapped consistently throughout the rejection for multiple lower surfaces with respect to a same assembly orientation, regardless of the final resultant orientation.) is supported by the plurality of capacitors (indirectly supported); and
stacking one or more additional second semiconductor dies (404; [0079]: “one or more stacks of dies 404”; [0083]: “dies 404 may be memory dies” requires at least some semiconductor material to function, thus a semiconductor die) on the second semiconductor die (directly on).
Illustrated below are marked and annotated figures of a first interpretation (Interpretation A) of Figs. 5A and 16 of Yu.
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Regarding claim 3, Yu discloses the method of claim 1 (Fig. 4A), further comprising:
planarizing an upper surface of the encapsulant material ([0050]: “a planarization process”) before attaching the second semiconductor die to the first semiconductor die and the plurality of capacitors (“before” is shown by progressing from the method step of Fig. 4A to Fig. 16),
wherein the planarized upper surface of the encapsulant material is configured to at least partially support (indirectly support) the second semiconductor die on a level surface (Note: The planarized upper surface is integral to assembly 300 which ultimately supports 402).
Regarding claim 4, Yu discloses the method of claim 3 (Fig. 5A) wherein the planarized upper surface of the encapsulant material is coplanar with a top surface of the first semiconductor die (See annotated Fig. 5A. Note: these surfaces are “coplanar” because they mutually interface at the same plane), wherein the top surface of the first semiconductor die at least partially supports the second semiconductor die (Note: The top surface is integral to assembly 300 which ultimately supports 402).
Regarding claim 5, Yu discloses the method of claim 1 (Fig. 16) wherein stacking the one or more additional second semiconductor dies to the second semiconductor die includes positioning the one or more additional second semiconductor dies to generally evenly distribute a weight of the one or more additional second semiconductor dies among the plurality of capacitors (the weight of 404 is distributed among the completed assembly 300 which integrally includes the capacitors 80, thus “generally evenly”).
Regarding claim 6, Yu discloses the method of claim 1 (Fig. 5A) wherein each of the plurality of capacitors has an upper surface (See annotated Fig. 5A) that is parallel with a top surface of the first semiconductor die (parallel at the same plane).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claim 1 above, and further in view of Takatsu (US 20060113679 A1).
Regarding claim 22, Yu discloses the method of claim 1, wherein at least partially encasing the plurality of capacitors with the encapsulant material comprises:
at least partially encasing a first capacitor with the encapsulant material ([0049]: “formed after placement of the memory device 60 and passive device 80”); and
at least partially encasing a second capacitor with the encapsulant material (the capacitors are pluralized within a single component 80, thus encapsulated in the same way; [0049]: “formed after placement of the memory device 60 and passive device 80”),
wherein the second capacitor is spaced apart from the first capacitor such that there is a gap between the encapsulant material at least partially encasing the first capacitor and the encapsulant material at least partially encasing the second capacitor.
Yu discloses the plurality of capacitors but fails to teach a gap included with their arrangement. Thus, Yu fails to teach “wherein the second capacitor is spaced apart from the first capacitor such that there is a gap between the encapsulant material at least partially encasing the first capacitor and the encapsulant material at least partially encasing the second capacitor”.
Takatsu discloses a method (Fig. 7) wherein the second capacitor (one of 127; [0038]: “a diode, a resistor, a capacitor and the like”) is spaced apart from the first capacitor (another of 127) such that there is a gap (the “gap” is occupied by die 155) between the encapsulant material at least partially encasing the first capacitor and the encapsulant material at least partially encasing the second capacitor.
Modifying the method (of Yu) to incorporate the duplicated capacitor and the gap arrangement of Takatsu would arrive at the claimed method and semiconductor device configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success incorporating an additional capacitor with the claimed gap arrangement because: 1) this configuration and arrangement is a duplication and arrangement of similar parts (Takatsu: Fig. 7: duplicated components 127 correspond to the Yu: Fig. 5A: single component 80); and 2) these parts are encapsulated with the same method sequence (Takatsu: [0030]: “sealed by resin”; Yu: [0049]: “formed after placement of the memory device 60 and passive device 80”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed first and second capacitors and gap arrangement because the prior art shows this configuration is a duplication and arrangement of similar parts using similar methods. MPEP 2144.04 (VI)(B) and (C).
Claims 8-10, 12, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Takatsu.
Regarding independent claim 8, Yu discloses a method of manufacturing a semiconductor device (Fig. 3A), comprising:
attaching a bottom surface of a first semiconductor die (60; [0024]: “includes a semiconductor substrate”. See annotated Fig. 5A for surface designation) to a front side of a base substrate (20. See annotated Fig. 5A for side designation),
wherein the first semiconductor die includes a first upper surface (See annotated Fig. 5A for surface designation) opposite the bottom surface and facing away from the base substrate;
electrically coupling (coupled by 88) a first lower surface (See annotated Fig. 5A for surface designation) of a first passive electrical component (80; [0026]: “includes passive devices…capacitors”) to the front side of the base substrate adjacent to a first side the first semiconductor die (See annotated figure for side designation), wherein the first passive electrical component includes a second upper surface (See annotated Fig. 5A for surface designation) opposite the first lower surface and facing away from the base substrate;
electrically coupling a second lower surface of a second passive electrical component to the front side of the base substrate adjacent to a second side of the first semiconductor die opposite the first side such that the semiconductor die is positioned between the first passive electrical component and the second passive electrical component,
wherein the second passive electrical component includes a third upper surface (See annotated Fig. 5A for surface designation) opposite the second lower surface and facing away from the base substrate;
forming an encapsulant (104) over the base substrate and at least partially around (horizontally around) the first passive electrical component and the second passive electrical component, wherein forming the encapsulant includes planarizing ([0050]: “a planarization process”) a fourth upper surface of the encapsulant (See annotated Fig. 5A for surface designation) to be coplanar with the first upper surface of the first semiconductor die (coplanar is shown); and
stacking a plurality of second semiconductor dies (Fig. 16: 402, 404) over the encapsulant (vertically over), the second upper surface of the first passive electrical component (vertically over), and the third upper surface of the second passive electrical component (vertically over),
wherein the plurality of second semiconductor dies form a die stack having a longitudinal footprint (Second Longitudinal Footprint. See annotated Fig. 16), and wherein the first semiconductor die, the first passive electrical component, and the second passive electrical component are each positioned fully within the longitudinal footprint (Each are fully within the second footprint).
Illustrated below are marked and annotated figures of a second interpretation (Interpretation B) of Figs. 5A and 16 of Yu.
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Yu only illustrates a single passive electrical component capable of including the claimed encapsulant sequence. Thus, Yu fails to teach:
“electrically coupling a second lower surface of a second passive electrical component to the front side of the base substrate adjacent to a second side of the first semiconductor die opposite the first side such that the semiconductor die is positioned between the first passive electrical component and the second passive electrical component,
[…]
forming an encapsulant over the base substrate and at least partially around the first passive electrical component and the second passive electrical component…”.
Takatsu discloses a method of manufacturing a semiconductor device (Fig. 7), comprising:
electrically coupling a second lower surface of a second passive electrical component (one of 127; [0038]: “a diode, a resistor, a capacitor and the like”) to the front side of the base substrate (151) adjacent to a second side of the first semiconductor die (155) opposite the first side such that the semiconductor die is positioned between the first passive electrical component (another of 127) and the second passive electrical component,
[…]
forming an encapsulant (134) over the base substrate and at least partially around the first passive electrical component and the second passive electrical component ([0030]: “sealed by resin”).
Modifying the method (of Yu) to incorporate the duplicated passive electrical component and the die arrangement of Takatsu would arrive at the claimed method and semiconductor device configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success incorporating an additional passive electrical component with the claimed die arrangement because: 1) this configuration and arrangement is a duplication and arrangement of similar parts (Takatsu: Fig. 7: duplicated components 127 correspond to the Yu: Fig. 5A: single component 80); and 2) these parts are encapsulated with the same method sequence (Takatsu: [0030]: “sealed by resin”; Yu: [0049]: “formed after placement of the memory device 60 and passive device 80”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed first and second passive electrical components and first semiconductor die arrangement because the prior art shows this configuration is a duplication and arrangement of similar parts using similar methods. MPEP 2144.04 (VI)(B) and (C).
Regarding claim 9, Yu in view of Takatsu discloses the method of claim 8 (Yu: Fig. 5A), wherein the second upper surface of the passive electrical component is coplanar with the first upper surface of the first semiconductor die (the surfaces selected as the first, second, third, and fourth upper surfaces are coplanar with each other), and wherein stacking the plurality of second semiconductor dies comprises attaching a bottom surface (See annotated Fig. 16 for surface designation) of a lowermost second semiconductor die (402) to the first upper surface of the first semiconductor die (indirectly attaching) and the second upper surface of the passive electrical component (indirectly attaching).
Regarding claim 10, Yu in view of Takatsu discloses the method of claim 8, wherein stacking the plurality of second semiconductor dies comprises attaching a bottom surface (Yu: See annotated Fig. 16 for surface designation) of a lowermost second semiconductor die (402) to at least a portion of the encapsulant (indirectly attaching).
Regarding claim 12, Yu in view of Takatsu discloses the method of claim 8 (Yu: Fig. 5A) wherein the second upper surface and the third upper surface are each coplanar with the first upper surface and the fourth upper surface (the surfaces selected as the first, second, third, and fourth upper surfaces are coplanar with each other).
Regarding independent claim 15, Yu discloses a method of forming a stacked semiconductor device (Fig. 3A), the method comprising:
mounting a plurality of capacitors (80; [0027]: “includes passive devices…capacitors”. Note: a single capacitor is relied upon here. See Takatsu regarding “a plurality”.) to a base substrate (20) around a central portion of the base substrate (See annotated Fig. 5A for portion designation),
wherein mounting the plurality of capacitors to the base substrate comprises individually physically (directly physically) and electrically coupling (coupled by 88) each of the plurality of capacitors to the base substrate, and
wherein mounting the plurality of capacitors comprises mounting a first capacitor (80) to the base substrate adjacent to a first side of the central portion (See annotated figure for side designation) and mounting a second capacitor to a second side of the central portion opposite the first side;
individually encasing each of the plurality of capacitors in an encapsulant material (104; as shown in the method step of Fig. 4A);
mounting a first semiconductor die (60) to the central portion of the base substrate,
wherein mounting the first semiconductor die to the base substrate comprises physically (directly physically) and electrically coupling (coupled by 68) a lower surface of the first semiconductor die (See annotated Fig. 5A for surface designation) to the base substrate; and
stacking one or more second semiconductor dies (Fig. 16: 402, 404) over (vertically indirectly over) the first semiconductor die and the plurality of capacitors,
wherein the one or more second semiconductor dies forms a die stack having a longitudinal footprint (Second Longitudinal Footprint. See annotated Fig. 16), and wherein the first semiconductor die and each of the plurality of capacitors is positioned within the longitudinal footprint (Each are fully within the second footprint).
Illustrated below are marked and annotated figures of a third interpretation (Interpretation C) of Figs. 5A and 16 of Yu.
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Yu fails to teach the method including the claimed number or arrangement of capacitors “mounting a second capacitor to a second side of the central portion opposite the first side” because Yu illustrates only the first capacitor. Thus: Yu fails to teach “mounting a plurality of capacitors to a base substrate around a central portion of the base substrate, wherein mounting the plurality of capacitors to the base substrate comprises individually physically and electrically coupling each of the plurality of capacitors to the base substrate, and wherein mounting the plurality of capacitors comprises mounting a first capacitor to the base substrate adjacent to a first side of the central portion and mounting a second capacitor to a second side of the central portion opposite the first side;
individually encasing each of the plurality of capacitors in an encapsulant material;
mounting a first semiconductor die to the central portion of the base substrate, wherein mounting the first semiconductor die to the base substrate comprises physically and electrically coupling a lower surface of the first semiconductor die to the base substrate; and
stacking one or more second semiconductor dies over the first semiconductor die and the plurality of capacitors, wherein the one or more second semiconductor dies forms a die stack having a longitudinal footprint, and wherein the first semiconductor die and each of the plurality of capacitors is positioned within the longitudinal footprint”.
Takatsu discloses a method of forming a stacked semiconductor device (Fig. 7), the method comprising:
mounting a plurality of capacitors (127, multiples) to a base substrate (151) around a central portion of the base substrate (J), wherein mounting the plurality of capacitors to the base substrate comprises individually physically and electrically coupling each of the plurality of capacitors to the base substrate (127 are separate and distinct capacitors, thus “individually”), and
wherein mounting the plurality of capacitors comprises mounting a first capacitor (one of 127) to the base substrate adjacent to a first side of the central portion and mounting a second capacitor (another of 127) to a second side of the central portion opposite the first side.
Modifying the number and arrangement of the capacitor arrangement of Yu by incorporating the configuration of Takatsu would arrive at the claimed capacitor configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: in each situation at least the first capacitors share a similar configuration (Yu: Fig. 5A; Takatsu: Fig. 7); and Takatsu teaches arrangement may be varied (Figs. 1 and 7 teach different arrangements). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed capacitor configuration because it is a duplication of parts and rearrangement of parts encompassed elsewhere in the prior art. MPEP 2144.04 (VI)(B) and (C).
Illustrated below is Fig. 7 of Takatsu.
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Regarding claim 16, Yu in view of Takatsu discloses the method of claim 15 (Yu: Fig. 16) wherein:
stacking the one or more second semiconductor dies over the first semiconductor die and the plurality of capacitors comprises
attaching a lowermost second semiconductor die (402) to a first upper surface of each of the plurality of capacitors (indirectly attaching) and a second upper surface of the first semiconductor die (indirectly attaching),
wherein the second upper surface is coplanar with the first upper surface of each of the plurality of capacitors (the surfaces selected as the first and second upper surfaces are coplanar with each other).
Regarding claim 17, Yu in view of Takatsu discloses the method of claim 15 (Yu: Fig. 16)
wherein stacking the one or more second semiconductor dies over the first semiconductor die and the plurality of capacitors includes attaching (indirectly attaching) a lowermost die (402) to a plurality of first upper surfaces of the encapsulant material (See annotated Fig. 5A) around each of the plurality of capacitors and a second upper surface of the first semiconductor die (See annotated Fig. 5A),
wherein the second upper surface is coplanar with the plurality of first upper surfaces of the encapsulant material around each of the plurality of capacitors (the surfaces selected as the first upper surfaces of the encapsulant material and the second upper surface are coplanar with each other).
Regarding claim 18, Yu in view of Takatsu discloses the method of claim 17 (Yu: Fig. 4A), wherein individually encasing each of the plurality of capacitors in the encapsulant material comprises planarizing the plurality of first upper surfaces of the encapsulant material ([0050]: “a planarization process”. Note: this process of Yu is reasonably applied to the pluralized capacitor arrangement of Yu in view of Takatsu) to lower a height of the plurality of first upper surfaces with respect to the base substrate ([0050]: “The planarization process is performed on…the first dielectric layer 104”).
Regarding claim 19, Yu in view of Takatsu discloses the method of claim 15 (Yu: Fig. 5A), further comprising mounting one or more spacers to the base substrate (40. Note: 40 is occupying a space between 400 and 20, thus a spacer) in a position that is peripheral to at least one of the plurality of capacitors with respect to the central portion (40 and 80 are positioned differently with respect to the Central Portion, thus “peripheral”), wherein the one or more spacers are configured to at least partially support the die stack (indirectly supported).
Regarding claim 20, Yu in view of Takatsu discloses the method of claim 15 (Yu: Fig. 16) wherein: stacking the one or more second semiconductor dies over the first semiconductor die and the plurality of capacitors places a lowermost second semiconductor die (402) in contact with each of the plurality of capacitors (indirect contact) and the first semiconductor die (indirect contact).
Allowable Subject Matter
Claim 21 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claim 21 is the inclusion of the limitation “wherein a first semiconductor die on the front side of the semiconductor package substrate within the central portion comprises positioning the lower surface of the first semiconductor die facing the semiconductor package substrate and positioning an upper surface of the first semiconductor die opposite the lower surface beneath or level with a top surface of each of the plurality of capacitors” in combination with the other limitations in the claim. For example, the prior art of record teaches all of the claimed sequences, but the prior art does not simultaneously teach or suggest the claimed arrangement. The claimed arrangement is a resultant arrangement produced by a method configuration different from the teachings and suggestions found in the cited references and elsewhere in the prior art, when considered in combination with all other limitations in claims 21 and 1.
The primary reason for the allowable subject matter of claim 23 is the inclusion of the limitation “wherein positioning the first semiconductor die on the front side of the semiconductor package substrate comprises bonding the lower surface of the first semiconductor die directly to the central portion” in combination with the other limitations in the claim. For example, the prior art of record teaches all of the claimed sequences, but the prior art does not simultaneously teach or suggest the claimed arrangement. The claimed arrangement is a resultant arrangement produced by a method configuration different from the teachings and suggestions found in the cited references and elsewhere in the prior art, when considered in combination with all other limitations in claims 23 and 1.
Response to Arguments
Applicant's arguments filed 7/23/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to claim 1 that “Yu fails to disclose or suggest each and every feature of claim 1 including, among other features, “individually placing each of a plurality of capacitors on a front side of a semiconductor package substrate adjacent to a central portion of the front side.” In contrast to these features, Yu only ever discloses bonding the passive device to the first processor device 20 as a unit, rather than "individually placing each of a plurality of capacitors" as required by independent claim 1”. Remarks at pg. 12.
Examiner’s reply:
The examiner disagrees and points to MPEP 2111: Broadest Reasonable Interpretation. The examiner finds the claim as written reasonably including configurations and placements of capacitors (a single collective plurality, and each of the single pluralities is placed) beyond the configurations and placement sequences disclosed by Applicant (individual discrete capacitors separately and arguably sequentially placed). Accordingly, the examiner maintains the rejection in the same way as before.
Applicant argues:
Applicant argues with respect to claim 4 that “Applicant respectfully submits that the spatially relative terms should be interpreted consistently within an orientation such that having selected one orientation to identify the “planarized upper surface of the encapsulant material,” the orientation should be consistent when identifying the “top surface of the first semiconductor die,” rather than inverted to effectively ignore features recited in the claims”. Remarks at pg. 13.
Examiner’s reply:
The examiner does not find Applicant’s remarks persuasive because “top surface” as claimed could reasonably be related to an absolute direction of all components collectively within the resultant device, a direction relating a component to a corresponding manufacturing step (i.e., “top” in relation to a chip carrier on the “bottom”), or to a functional configuration of a component (i.e., an active surface of a semiconductor die could reasonably also be called the “top surface”). Since the claim does not require any particular relation between these separate directional designations (i.e., “top” and “upper”), the claim as written reasonably includes a plurality of “top surface” configurations beyond the contended configuration (MPEP 2111). Accordingly, the examiner maintains the rejection in the same way as before.
Applicant argues:
Applicant argues with respect to amended claim 8 that “the first conductive vias 106 in Yu can only be formed after the first dielectric layer 104 is formed”. Remarks at pg. 14.
Examiner’s reply:
Applicant’s arguments with respect to amended claim 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Takatsu is relied upon to render obvious the claimed method sequence.
Applicant argues:
Applicant argues with respect to claim 15 that “Yu encases all of the components of the integrated circuit package 100 when it is formed, rather than individually encasing discrete parts, such as a plurality of capacitors as modified, arguendo, in view of Takatsu.
The examiner disagrees and points to MPEP 2111: Broadest Reasonable Interpretation. The examiner finds the claim as written reasonably including method sequences (individual separate and discrete capacitors that are each encased, and therefore individually encased) beyond the sequences disclosed by Applicant (individual discrete capacitors separately and arguably sequentially encased). Accordingly, the examiner maintains the rejection in the same way as before.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
Prosecution Insights