DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species of figure 17, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/13/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,3,4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Furihata (20170179154)in view of Arai (20100159657) and Evidenced by Mason 2008 Ch13 “Memory Basics”
A. As to claim 1 and 3, Furihata teaches A semiconductor device comprising: a first chip including: a first substrate (Figure 17c bottom item 700 including the substrate 9); and a logic circuit provided on the first substrate (item 700); a second chip provided above the first chip (regions 110 -165), bonded to the first chip (See figure 17C bonded is product by process but it is bonded), and including: a plurality of electrode layers provided above the logic circuit and stacked in a first direction( item 146); a first semiconductor layer extending in the first direction in the plurality of electrode layers (one of the item 27one of 602 figure 10a); a second semiconductor layer extending in the first direction in the plurality of electrode layers (another of the items 602 figure 10a); a metal layer provided above an uppermost layer of the plurality of electrode layers (item 103); a third semiconductor layer connecting the metal layer and the first semiconductor layer One of the item s 63); and a fourth semiconductor layer (another of the items 63) connecting the metal layer and the second semiconductor layer )see associated figures); and a bonding metal provided on a bonding surface of the first chip and the second chip (item 6 paragraph 169), the first semiconductor layer and the logic circuit being electrically connected via the bonding metal (see figures); Furihata does not explicitly teach wherein the third semiconductor layer includes an impurity and has an impurity concentration higher than an impurity concentration of the first semiconductor layer, and the fourth semiconductor layer includes an impurity and has an impurity concentration higher than an impurity concentration of the second semiconductor layer. Furihata teaches metal lines between the nand the logic (item 780 ) . Such a structure could function as a bit line and applicant gives no structure of circuitry that would make it definable as a bit line ( page 4 of the original disclosure). Thus, portions of Furihata item 780 can be considered a bit line since there is only a discussion of desired use and not specificity of how to implement the lines a bit line
Arai teaches a columnar channel for a nand device comprising a lightly doped channel and highly doped source or drains on top and bottom connect to metal lines above and below the channel. Both the lightly doped portions and the heavily doped portion are columnar.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to provide the source and drains as higher doped regions thus optimizing the functionality of device for the desired operation scheme (normally on type device vs normally off).
Contrary to the arguments provided applicant bit line is an intended usage of wires. Specifically, page 14--22 discusses the circuitry needed to make the “bit lines” a bit line without the associated circuitry the entire recitation of “bit line” is an intended usage. Further it is noted applicant does not even recite a memory structure and that the bit lines are associated with the memory. So, the entire recitation of bit line is intended usage.
B. As to claims 4 and 6 Arai further suggest further comprising a conductive layer provided above an uppermost electrode layer among the plurality of electrode layers, and extending to cross the first direction (item 7).
Thus, it would have to one of ordinary skill in the art at the time of filing to provide a metal conductive layer to connect the lines at the top for the desired modes of operation.
C. As to claim 21, without the associated circuitry as evidenced by Mason what is a “source layer” or a “bit line” is entirely arbitrary since the layers of 103 could function as a “source layer” then 103 can be consider a source layer. Layer 103 is electrically connected to 602.
Allowable Subject Matter
Claim 2, 5,7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior art fails to teach in combination with the other elements of claim 1 and for claim 5 claims 1 and 5:
Claim 2: comprising, as the first semiconductor layer, a plurality of first semiconductor layers provided in an array in an in-plane direction of the plurality of electrode layers, wherein the second semiconductor layer is electrically connected to each of the plurality of first semiconductor layers.
Claim 5: further comprising a conductive layer provided above an uppermost electrode layer among the plurality of electrode layers, and extending to cross the first direction.
Claim 7: wherein the second semiconductor layer annularly surrounds the first semiconductor layer.
Response to Arguments
Applicant's arguments filed 12/3/2025 have been fully considered but they are not persuasive. Applicant argues that Furihata layers 780 are not bit lines. In response to applicant's argument that “bit line”, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
The phrase “bit line” is an intended usage without recitations of the proper circuitry (see Mason) Column Circuitry, sense amplifiers and appropriate power access transistors. Without these the recitation is intended usage. It is further noted applicant does not even recite a memory structure claim 1 is drawn to a plurality of electrode layers that are provided above the first substrate and are stacked in a first direction; further the “bit lines” are not even associated with the plurality of electrodes: a plurality of bit lines provided between the first substrate and a lowermost electrode layer among the plurality of electrode layers in the first direction, and each extending to cross the first direction. The rest of claim does not relate the bit lines to any of the structure: a plurality of columnar portions, each of which extends in the first direction in the plurality of electrode layers and includes a first semiconductor layer; and a second semiconductor layer provided to contact the first semiconductor layer in each of the plurality of columnar portions, wherein the second semiconductor layer includes an impurity diffusion layer that has an impurity concentration higher than an impurity concentration of the first semiconductor layer.
There is no additional relationship between the bit lines and any other structure much less a memory structure. Thus 780 could act as a bit line whether it be for the memory stack or some other non-claimed memory. A bit lines only requirement is that it is conductive which items 780 are.
Likewise, the claim 21 does not clarify what is a source line. Specifically, where the associated transistor with the source is located and is likewise intended usage.
Applicant is reminded the office is not limited to the interpretations provided in the reference the office may take the broadest reasonable interpretation. Since applicant has not associated the bit lines with any memory or peripheral circuitry to make te bit lines function as bit lines elements 780 may be used as a bit line and item 103 maybe used as a source line.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F. Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/ Primary Examiner, Art Unit 2896