CTNF 18/588,760 CTNF 101592 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 1-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kotra et al. (US 20210034256 A1) in view of Borkar et al. (US 20070070673 A1) and Teig et al. (US 20190123024 A1) . Regarding claim 1, Kotra et al. (US 20210034256 A1) teaches a 3D chip stack structure comprising: a first chip ( 102 ) comprising a first number of core units ( 111 ) and a first number of cache units ( 112 ), and having power elements ( 110 , allows for communication and addressing ) located between each neighboring core unit of the first chip [Fig. 1, ¶¶0021-0022]; a second chip ( 103 ) comprising a second number of core unit ( 113 ) and a second number of cache units ( 114 ) [¶0013], and having a heat spreader element located on at least one of the core units of the second chip [¶0014, the temperatures are spread through the layer which can show there is a heat spreader element in the layer], wherein the first chip and the second chip are stacked one on top the other [¶0012]; a power via ( 110 ) connecting one of the power elements of the first chip to one of the core units of the second chip [¶0012]. Kotra et al. doesn’t teach a heat spreader element and thermal via. Borkar et al. teaches having a heat spreader element located on at least one of the core units of the second chip [¶0027, heat spreader attached to core processor] and a thermal via ( heat pipe ) connecting one of the core units of the first chip to one of the heat spreader elements of the second chip [¶0027, showcases there is connection between two areas] It would have been obvious for a person of ordinary skill in the art to combine the 3D chip stack structure taught by Kotra et al. and the heat spreader taught by Borkar et al. because it is beneficial for the system to have a designated system that would allow for the dispersion of heat from the stacked chip structure with ease and the heat pipe allows for direct connection between layers that would allow for the transmission of heat to smoother. Kotra et al. in view of Borkar et al. doesn’t teach the chips being stacked in a staggered manner. Teig et al. teaches the chips being stacked in a staggered manner [Fig. 2, ¶0108, where the core unit of one chip is over the memory unit of the other]. It would have been obvious for a person of ordinary skill in the art before the effective filing date to combine the 3D chip stack structure as taught by Kotra et al. in view of Borkar et al. with the staggered stacking of Teig et al. because this formation can reduce the size of the arrangement [Teig et al., ¶¶0021 and 0054] Regarding claim 2, Kotra et al. in view of Borkar et al. and Teig et al. (US 20230402098 A1) teaches the 3D chip stack structure of Claim 1, wherein the first chip ( 102 ) is located beneath the second chip ( 103 ) [Fig. 1, ¶0012, Kotra et al.]. Regarding claim 3, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 2, wherein a frontside of the first chip faces a frontside of the second chip [as seen in attached Fig.1, Kotra et al.]. PNG media_image1.png 505 541 media_image1.png Greyscale Regarding claim 4, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 2, wherein a backside of the first chip faces a backside of the second chip [as seen in attached Fig. 1 below, Kotra et al.]. PNG media_image2.png 505 541 media_image2.png Greyscale Regarding claim 5, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 2, wherein a frontside of the first chip faces a backside of the second chip [as seen in attached Fig. 1 below, Kotra et al.]. PNG media_image3.png 505 541 media_image3.png Greyscale Regarding claim 6, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 2, wherein a backside of the first chip faces a frontside of the second chip [as seen in attached Fig. 1 below, Kotra et al.]. PNG media_image4.png 505 541 media_image4.png Greyscale Regarding claim 7, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 1, wherein the first chip is located above the second chip [Fig. 1 as seen below, the top can be seen as where processor 101 is, so layer 102 would be above 103, Kotra et al.]. PNG media_image5.png 505 541 media_image5.png Greyscale Regarding claim 8, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 7, wherein a frontside of the first chip faces a frontside of the second chip [as seen in attached Fig. 1 below, Kotra et al.]. PNG media_image6.png 505 541 media_image6.png Greyscale Regarding claim 9, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 7, wherein a backside of the first chip faces a backside of the second chip [as seen in attached fig. 1 below, Kotra et al.]. PNG media_image7.png 505 541 media_image7.png Greyscale Regarding claim 10, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 7, wherein a frontside of the first chip faces a backside of the second chip [as seen in attached fig. 1 below, Kotra et al.]. PNG media_image8.png 505 541 media_image8.png Greyscale Regarding claim 11, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 7, wherein a backside of the first chip faces a frontside of the second chip [as seen in attached fig. 1 below, Kotra et al.]. PNG media_image9.png 505 541 media_image9.png Greyscale Regarding claim 12, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 1, further comprising a dielectric material structure encasing the first chip, the second chip, the power via and the thermal via [¶0034, Teig et al. encapsulated by epoxy or chip case]. Regarding claim 13, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 1, wherein the first number is different from the second number [Fig. 4, ¶0079, figure shows the different numbers for the core units and cache units of the first and second chips, Teig et al.]. Regarding claim 14, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 1, wherein the first chip has a size that is different from a size of the second chip [¶0067, for the first chip the circuits are smaller and fewer which would make the chip size smaller, Teig et al.]. Regarding claim 15, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 1, further comprising a gap between each cache unit within a row of caches units of both the first chip and the second chip [Fig. 1, ¶0013, there are different regions and as seen in the figure there are spaces between the different units, Kotra et al.]. Regarding claim 16, Kotra et al. in view of Borkar et al. and Teig et al. teaches the 3D chip stack structure of Claim 1, wherein each core unit of the second chip lies between a pair of neighboring cache units of the first chip [Fig. 4, ¶0073, partially overlapping of the cache and cores of the first and second die, which means that the core units are between neighboring cache units of the first chip, Teig et al.] . 07-21-aia AIA Claim (s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kotra et al. (US 20210034256 A1) in view of Borkar et al. (US 20070070673 A1) and Devaux (US 20230260968 A1) . Regarding claim 17, Kotra et al. teaches a 3D chip stack structure comprising: a first chip ( 102 ) comprising a first number of core units ( 111 ) and a first number of cache units ( 112 ), and having power elements ( 110 , allows for communication and addressing ) located between each neighboring core unit of the first chip [Fig. 1, ¶¶0021-0022]; a second chip ( 103 ) comprising a second number of core unit ( 113 ) and a second number of cache units ( 114 ) [¶0013], and having a heat spreader element located on at least one of the core units of the second chip [¶0014, the temperatures are spread through the layer which can show there is a heat spreader element in the layer], wherein the first chip and the second chip are stacked one on top the other [¶0012], a power via ( 110 ) connecting one of the power elements of the first chip to one of the core units of the second chip [¶0012]. Kotra et al. doesn’t teach a heat spreader element and thermal via. Bokar et al. teaches having a heat spreader element located on at least one of the core units of the second chip [¶0027, heat spreader attached to core processor] and a thermal via ( heat pipe ) connecting one of the core units of the first chip to one of the heat spreader elements of the second chip [¶0027, showcases there is connection between two areas]. It would have been obvious for a person of ordinary skill in the art to combine the 3D chip stack structure taught by Kotra et al. and the heat spreader taught by Borkar et al. because it is beneficial for the system to have a designated system that would allow for the dispersion of heat from the stacked chip structure with ease and the heat pipe allows for direct connection between layers that would allow for the transmission of heat to smoother. Devaux (US 20230260968 A1) teaches the 3D chip stacked in a staggered manner, and the core units of the first chip are located on the periphery of the first chip, and the core units of the second chip are located on the periphery of the second chip [Fig. 11, ¶¶0067-0068, the figure showcases the staggered stacking and the circuit constituted by the CPU processor is seen to be in the peripheral areas]. It would have been obvious to a person of ordinary skill in the art before the effective filing date to combine the teachings of Kotra et al. in view of Bokar et al. with the staggered stacking and core locations as taught by Devaux because the formation may benefit with the release of excessive heat [Devaux, ¶0049]. Regarding claim 18, Kotra et al. in view of Borkar et al. and Devaux teaches the 3D chip stack structure of Claim 17, wherein the first chip ( 102 ) is located beneath the second chip ( 103 )[Fig. 1, Kotra et al.]. Regarding claim 19, Kotra et al. in view of Borkar et al. and Devaux teaches the 3D chip stack structure of Claim 17, wherein the first chip ( 102 ) is located above the second chip ( 103 ) [Fig. 1 as seen below, the top can be seen as where processor 101 is, so layer 102 would be above 103, Kotra et al.]. PNG media_image5.png 505 541 media_image5.png Greyscale Regarding claim 20, Kotra et al. in view of Borkar et al. and Devaux teaches the 3D chip stack structure of Claim 1, further comprising a dielectric material structure encasing the first chip, the second chip, the power via and the thermal via [¶0070, Devaux]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NOOR MOHAMMAD ISMAIL TAHIR whose telephone number is (571)272-6166. The examiner can normally be reached Monday Friday, 8 a.m. 5 p.m. ET.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NOOR MOHAMMAD ISMAIL TAHIR/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893 Application/Control Number: 18/588,760 Page 2 Art Unit: 2893 Application/Control Number: 18/588,760 Page 3 Art Unit: 2893 Application/Control Number: 18/588,760 Page 4 Art Unit: 2893 Application/Control Number: 18/588,760 Page 5 Art Unit: 2893 Application/Control Number: 18/588,760 Page 6 Art Unit: 2893 Application/Control Number: 18/588,760 Page 7 Art Unit: 2893 Application/Control Number: 18/588,760 Page 8 Art Unit: 2893 Application/Control Number: 18/588,760 Page 9 Art Unit: 2893 Application/Control Number: 18/588,760 Page 10 Art Unit: 2893 Application/Control Number: 18/588,760 Page 11 Art Unit: 2893
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