Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, drawn to a bonded memory assembly including center input/output pads, (claims 1-15) in the reply filed on 07/17/2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the tapered shape of the sidewall of the through-stack via structure of claim 15 must be shown or the feature canceled from the claim. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chowdhury et al. US 20200235090.
Regarding claim 1, Chowdhury discloses a bonded assembly, comprising:
a memory die (element 900, described in paragraph [0136] comprising:
an alternating stack of insulating layers and electrically conductive layers (paragraph [0036] discloses a stack of alternating insulating layers 32 and electrically conductive layers 46);
memory-side dielectric material layers embedding memory-side metal interconnect structures and memory-side bonding pads (figure 14A shows memory-side dielectric layers 181,183 with embedded memory-side metal interconnect structures including 186 and 188 [0136] and memory-side bonding pads 144 [0136]);
memory stack structures each comprising a memory film and a vertical semiconductor channel vertically extending through the alternating stack in a memory array region (paragraph [0136] discloses memory stack structures 55 comprising memory film 50 and vertical semiconductor channel 60 vertically extending through the alternating stack of layers 32 and 46 in the memory array region);
layer contact via structures contacting a respective electrically conductive layer within the alternating stack in a contact region (paragraphs [0110-0112] disclose layer contact via structures 86 contacting a respective electrically conductive layer 46 within the alternating stack 32/46 in a contact region, figure 14A);
a through-stack via structure (comprising vias 76, 184, 114, 124, 134 [0127]) vertically extending through a vertically-extending opening in the alternating stack within a center region of the memory die, which comprises a volume within the memory die that is more proximal to a geometrical center of the memory die than to a periphery of the memory die defined by outer sidewalls of the memory die in a plan view along a vertical direction (see annotated figure 14A, where this geometry is illustrated); and
a backside conductive pad discloses electrically contacting the through-stack via structure (paragraph [0127] discloses memory-side bonding pad 144A electrically connected to the through stack via 76, 184, 114, 124, 134); and
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a logic die (element 700 [0128], see 15a which shows the logic part on top of the memory of 14a) comprising a peripheral circuit ([0129])and logic-side bonding pads which are bonded to the memory-side bonding pads (paragraph [0132] discloses logic-side bonding pads 788 configured to mate with the memory-side bonding
pads 144 to provide electrically conductive paths between the memory die 900 and the logic die 700).
Regarding claim 2, Chowdhury discloses the bonded assembly of claim 1, wherein the logic die further comprises logic-side dielectric material layers embedding logic-die metal interconnect structures and the logic-side bonding pads (paragraph [0132] discloses logic-chip dielectric layers 760, with logic-chip metal interconnect structures 780 embedded within the logic-chip dielectric layers 760 and logic-side bonding pads 788, as in figure 15A.)
Regarding claim 3, Chowdhury discloses the bonded assembly of claim 2, wherein the through-stack via structure (comprising vias 76, 184, 114, 124, 134) is electrically connected to a semiconductor device in the logic die (710, described in paragraph [0128-0129]) through a subset of the memory-side metal interconnect structures ([0136] discloses that logic semiconductor 710 is electrically connected to the source contact structure 76 through a subset of memory-side metal interconnect structures, including 144) and through a subset of the logic-die metal interconnect structures (paragraph [0135] discloses that logic die interconnect structures 780 are connected to at least one memory side bonding pad 144, also shown in figure 15A).
Regarding claim 4, Chowdhury discloses the bonded assembly of claim 3, wherein the semiconductor device in the logic die comprises an input/output control device (paragraphs [0129, 0131 and 0133] describe the input/output control device comprised by the logic die).
Regarding claim 5, Chowdhury discloses the bonded assembly of claim 1, wherein an end surface of the through-stack via structure is in direct contact with the backside conductive pad (see figure 14A, where an end surface of the through-stack via structure comprising vias 76, 184, 114, 124, 134 is in direct contact with the backside conductive pad 144).
Regarding claim 6, Chowdhury discloses the bonded assembly of claim 1, wherein:
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the memory die (900 figure 15A) further comprises at least one source-level material layer (61) that is more distal from an interface between the memory die and the logic die (interface between 900 and 700) than a most distal layer of the alternating stacks is from the interface (see annotated figure 15A below);
the at least one source-level material layer electrically contacts sidewalls of the vertical semiconductor channel (the source level material layer comprising 61, 11 and 10 is electrically contacts the vertical semiconductor channel 60 as shown in figure 11B); and
the through-stack via structure vertically (comprising vias 76, 184, 114, 124, 134 ) extends through an opening in the at least one source-level material layer (layer comprising 61, 11, 10, 616), and is electrically isolated from the at least one source-level material layer (616 is a dielectric layer formed from 10, and so is electrically isolated [0101]).
Regarding claim 7, Chowdhury discloses the bonded assembly of claim 6, wherein
the memory die further comprises a backside dielectric layer that is more distal from the interface than the at least one source-level material layer is from the interface (the farthest part of backside dielectric layer 44 is more distal to the interface than component of the source-level material layer 11, as seen in figure 14B), and wherein
the through-stack via structure vertically extends through an opening in the backside dielectric layer (the component of the through-stack via structure 76 extends through an opening in the backside dielectric layer 44, see figure 14A).
Regarding claim 8, Chowdhury discloses the bonded assembly of claim 7,
wherein the memory die further comprises a conductive source layer that is more distal from the interface than the backside dielectric layer is from the interface (conductive source layer 61 is more distal from the interface between the memory die 900 and the logic die 700 than the backside dielectric layer 44), and
wherein the backside conductive pad is located within an opening in the conductive source layer (the backside conductive pad 144 is located within the vertical opening 79 of the conductive source layer 61, interpreted as intersecting the vertical plane of the conductive source opening).
Regarding claim 12, Chowdhury discloses the bonded assembly of claim 1, wherein the peripheral circuit comprises:
word line drivers configured to drive a subset of the electrically conductive layers within the alternating stacks (paragraph [0129] discloses that the peripheral circuit can include a word line driver that drives word lines of the three-dimensional memory array, as embodied as the electrically conductive layers 46) ;
bit line drivers configured to drive bit lines that are located in the memory die (paragraph [0129] discloses a bit line driver that drives the bit lines 128 in the memory die 900) and electrically connected to first ends of a respective subset of the memory stack structures (paragraph [0141] describes the connection of bit-lines to at least one memory-side bonding pad); and
a source line driver configured to drive a conductive source layer that is located in the memory die and electrically connected to second ends of a respective plurality of the memory stack structures (paragraph [0129] discloses a source power supply circuit that provides power to source regions 61, located in the memory die and connected to the memory stack structures 55) .
Regarding claim 13, Chowdhury discloses the bonded assembly of claim 1, wherein the vertically-extending opening is entirely laterally surrounded by the alternating stack such that an entirety of the vertically-extending opening is located within an area of the alternating stack in the plan view (The plan view of figure 10A shows that trench 79 is vertically extending within an area of the alternating stack comprising layers 32 and 46).
Regarding claim 14, Chowdhury discloses the bonded assembly of claim 1, wherein the through-stack via structure is laterally spaced from a sidewall of the vertically-extending opening by a tubular dielectric spacer (figure 14A shows that through-stack via structure 76 is laterally spaced from a sidewall of the vertically-extending opening by a tubular dielectric spacer 74 [0105]).
Regarding claim 15, Chowdhury discloses the bonded assembly of claim 1, wherein a sidewall of the through-stack via structure is tapered relative to a vertical direction that is perpendicular to an interface between the memory die and the logic die such that the through-stack via structure has a respective variable horizontal cross-sectional area that decreases with a vertical distance from a horizontal plane including the interface (Figure 15A shows that the via structure 76, 184, 114, 124, 134 such that the cross-sectional area of portion 134 is greater than the cross-sectional area of 76, which is more vertically distant from the interface.)
Allowable Subject Matter
Claims 9, 10, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, the prior art does not teach or render obvious the bonded assembly of claim 8 wherein the conductive source layer and the backside conductive pad have a same material composition and a same thickness in the combination as claimed. The mapping of the prior art of Chowdhury to the limitations of claim 8 above, taught conductive source layer 61 and backside conductive pad layer 144, which could not have the same material composition, as one is a doped semiconductor material and the other is metal. Other prior art that added a conductive source layer was not obvious to combine with the disclosure of Chowdhurdy, and this conductive layer did not teach geometry consistent with the limitations of claims 1, 6, 7, and 8.
Regarding claim 10, the prior art does not teach or render obvious the bonded assembly of claim 8 wherein the memory die further comprises a backside passivation layer covering the conductive source layer and having an opening that overlies the backside conductive pad; and
the backside conductive pad comprises a solder bonding pad including a layer stack comprising a copper layer, a diffusion barrier layer, and an under-bump metallization layer in the combination as claimed. Chowdhurdy does not teach a backside conductive pad comprising the claimed layers or the backside passivation layer with the claimed geometry. Additional prior art cannot be used in combination with the disclosure of Chowdhurdy to render these limitations obvious.
Regarding claim 11, the prior art does not teach or render obvious the bonded assembly of claim 8 wherein the memory die further comprises: a bonding-level dielectric layer overlying the conductive source layer and the backside conductive pad; and a backside bonding pad embedded in the bonding-level dielectric layer and electrically connected the backside conductive pads wherein the backside bonding pad is configured for metal-to-metal bonding and has a physically exposed copper surface in the combination as claimed. Chowdhurdy does not teach a backside bonding pad embedded in the bonding-level dielectric layer and electrically connected the backside conductive pads wherein the backside bonding pad is configured for metal-to-metal bonding and has a physically exposed copper surface. There is no prior art that can be combined with the conductive source layer 61 and backside conductive pads 144 of Chowdhurdy to render these limitations obvious in the combination as claimed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lien et al. US 20230016518 discloses a similar bonded assembly of memory and logic dies with a similar through-stack via structure located near the middle of the memory die.
Sakakibara et al. US 20170025421 discloses a similar 3d memory with tapering through-stack vias.
Rajashekhar et al. US 20210242241, Chibvongodze et al. US 20200185039, and Liu et al. US 20140252363 all disclose metal conductive source layers in similar memory structures, but none of these layers are obvious to combine with the disclosure of Chowdhurdy.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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