Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of Group I, claims 1-13 in the reply filed on May 27th, 2026 is acknowledged. Non-elected invention of Group II, claims 14-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Group I, claims 1-13 as follows.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on February 27th, 2024 and June 09th, 2025 have been considered by the examiner.
Drawings
The drawings filed on 02/27/2024 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 2020/0144380, hereinafter as Hwan ‘380) in view of Mochizuki (US 2022/0028879, hereinafter as Moch ‘879).
Regarding Claim 1, Hwan ‘380 teaches a device structure, comprising:
an alternating stack of insulating layers (Fig. 25A, (ILD); [0028]) and electrically conductive layers (Fig. 25A, (EL); [0028]) that alternate along a vertical direction, wherein lateral extents of the electrically conductive layers vary in a staircase region;
memory openings (Fig. 24C, (trenches “T”); [0167]) vertically extending through the alternating stack;
memory opening fill structures (CVS; [0044]) located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel (see para. [0045]); and
a continuous etch-stop and blocking dielectric layer (Fig. 25, (36); [0146]) including blocking dielectric layer portions and an etch-stop dielectric layer portion, wherein the etch-stop dielectric layer portion continuously extends over at least a portion of the alternating stack in the staircase region with a stepped vertical cross-sectional profile (see Fig. 25A).
Thus, Hwan ‘380 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a metal oxide dielectric layer”.
Moch ‘879 teaches a metal oxide dielectric layer (a dielectric metal oxide such as aluminum oxide; see Fig. 11A, (44); [0099]-[0100]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Hwan ‘380 by having a metal oxide dielectric layer for the purpose of functions as a control gate dielectric for the control gates (see para. [0098]) or improving the etching selectivity (e.g. for the removal of the continuous electrically conductive material layer (see para. [0107])) as suggested by Moch ‘879.
Regarding Claim 2, Moch ‘879 teaches each of the blocking dielectric layer portions (44) comprises a respective pair of horizontally-extending blocking dielectric layer segments joined by a respective set of tubular blocking dielectric layer segments that laterally surround a respective one of the memory opening fill structures (see Fig. 15).
Regarding Claim 3, Moch ‘879 teaches each of the electrically conductive layers (46; [0106]) comprises: a planar top surface an entirety of which is contacted by an upper horizontally-extending blocking dielectric layer segment within a respective blocking dielectric layer portion (44); and a planar bottom surface an entirety of which is contacted by a lower horizontally-extending blocking dielectric layer segment within the respective blocking dielectric layer portion (see Fig. 15).
Regarding Claim 4, Moch ‘879 teaches all horizontally-extending segments of the etch-stop dielectric layer portion (44) have a first uniform thickness; and all horizontally-extending segments and all vertically-extending segments of the blocking dielectric layer portions (44) have a second uniform thickness (see Fig. 15).
Thus, Hwan ‘380 and Moch ‘879 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the first uniform thickness is greater than the second uniform thickness”.
However, it has been held to be within the general skill of a worker in the art to select the first uniform thickness is greater than the second uniform thickness on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
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A person of ordinary skills in the art is motivated to select the first uniform thickness is greater than the second uniform thickness in order to improve the performance of the memory device.
Regarding Claim 5, Hwan ‘380 teaches a retro-stepped dielectric material portion (Fig. 25A, (55); [0034]) located in the staircase region over the etch-stop dielectric layer portion (36), wherein the etch-stop dielectric layer portion is in contact with horizontal surface segments and vertical surface segments of a retro-stepped dielectric material portion (see Fig. 25A).
Regarding Claim 6, Hwan ‘380 teaches first vertically-extending segments of the etch-stop dielectric layer portion (36) have the first uniform thickness; and second vertically-extending segments of the etch-stop dielectric layer portion (36) have the second uniform thickness (see Fig. 25A).
Regarding Claim 7, Hwan ‘380 teaches each neighboring pair of horizontally-extending segments of the etch-stop dielectric layer portion is joined to each other by a combination of a respective one of the first vertically-extending segments of the etch-stop dielectric layer portion and a respective one of the second vertically-extending segments of the etch-stop dielectric layer portion (see Fig. 15A).
Regarding Claim 8, Moch ‘879 teaches each of the first vertically-extending segments of the etch-stop dielectric layer portion (44) contacts a sidewall of a respective one of the insulating layers within the alternating stack (see para. [0100]); and each of the second vertically-extending segments of the etch-stop dielectric layer portion (44) contacts a sidewall of a respective one of the electrically conductive layers (46) within the alternating stack (see Fig. 12A)).
Regarding Claim 9, Moch ‘879 teaches the continuous metal oxide etch-stop and blocking dielectric layer (44; [0099]) comprises aluminum oxide
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraph numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Dorfner et al. (US 2024/0339328 A1)
Zhu et al. (US 2019/0096810 A1)
Lee et al. (US 2015/0179663 A1)
Lee et al. (US 2013/0313627 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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