Prosecution Insights
Last updated: October 01, 2026
Application No. 18/588,902

SEMICONDUCTOR LIGHT EMITTING DEVICE AND A DISPLAY DEVICE

Non-Final OA §102§103
Filed
Feb 27, 2024
Priority
Jul 03, 2023 — RE 10-2023-0085581
Examiner
MILLER, ALEXANDER MICHAEL
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Electronics Inc.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
6 granted / 7 resolved
+17.7% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
39 currently pending
Career history
72
Total Applications
across all art units

Statute-Specific Performance

§103
65.3%
+25.3% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
11.6%
-28.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 7 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim and Specification Status The Examiner acknowledges the amendments to claims 7-9, 11 and 20 in the Applicant’s response dated 26 June 2026. The claim amendments have been addressed below. The Examiner acknowledges the cancellation of claims 22-23 in the Applicant’s response dated 26 June 2026. Election/Restrictions Applicant's election with traverse of Invention I, Species A, Modification C1 and Species Z1 in the reply filed on 26 June 2026 is acknowledged. The traversal is on the grounds that claim 1 is a generic or linking claim common to the alleged device species, that the specification describes Figs. 13, 15, 17 and 18 as variations of the first embodiment of Fig. 8, not as separate inventions and the reliance on the number, shape or configuration of layers does not establish patentable distinctness, that the alleged Z1/Z2 species relate to display device connections, not patentably distinct semiconductor light emitting devices, and that no serious search or examination burden has been established. With respect to the traversal that the specification describes Figs. 13, 15, 17 and 18 as variations of the first embodiment of Fig. 8, not as separate inventions and the reliance on the number, shape or configuration of layers does not establish patentable distinctness, this argument is not found persuasive because the species are independent and distinct wherein each of the Species C1, C2, C3 and C4, as shown in Figs. 13, 15, 17 and 18 respectively, would result in different light spectrum output based on the different variations. Furthermore, the Applicant’s argument does not show or discuss that Species C1, C2, C3 and C4 are obvious variants as required by the traversal of species as outlined in the restriction requirement therefore, they are independent and distinct, and the argument is not found to persuasive. With respect to the traversal that the alleged Z1/Z2 species relate to display device connections, not patentably distinct semiconductor light emitting devices, this argument is not found persuasive because even if the Species Z1 and Z2 relate to display device connections, the figures and descriptions of the species are disclosed in the disclosure of the instant application and the species are independent and distinct wherein each of the Species Z1 and Z2 as shown in Fig. 19 and Fig. 21 respectively, would alter the device properties resulting in different light spectrum output based on the different configurations and the presence of the connection electrode would change the configuration of connecting light emitting devices. Furthermore, the Applicant’s argument does not show or discuss that Species Z1 and Z2 are obvious variants as required by the traversal of species as outlined in the restriction requirement therefore, they are independent and distinct, and the argument is not found to persuasive. With respect to the traversal that no serious search or examination burden has been established, this argument is not found persuasive because, as outlined in the restriction requirement, the inventions require different classification searches in at least CPC H10H 20/8314 and CPC H10H 29/03 and furthermore, the species require different fields of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries), and searching for a particular number, shape and configuration of metal and insulating layers in a semiconductor light emitting device as well as devices comprising a connection electrode is unlikely to yield results for a semiconductor light emitting device comprising a different number, shape and configuration of metal and insulating layers as well as the absence of a connection electrode, additionally upon conducting a search for the elected Invention, Species and Embodiments, the Examiner was not able to find prior art related to the non-elected Inventions, Species and Embodiments, and furthermore the Applicant has not provided any evidence on the record that there would be no search and or examination burden when searching between the patentably independent and distinct Inventions, Device Species, and Device Modifications, therefore the argument is not found to persuasive. With respect to the argument that claim 1 is generic or a linking claim common to the alleged species, the Examiner concedes that Claim 1 as it currently stands may appear to be generic to the alleged device species and therefore claim 1 will be examined on its merits. However, the restriction requirement between Inventions I and II, Device Species A and B, Device Modifications C1, C2, C3 and C4, and Device Species Z1 and Z2, is still deemed proper and is therefore made FINAL. Claims 5-6, 10 and 12-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Invention (II), Species (B), Modification (C2, C3 and C4) and Species (Z2), there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 26 June 2026. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) submitted on 27 February 2024 and 7 November 2025 have been considered by the examiner and made of record in the application file. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-4, 8-9 and 11 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by Tung-Lin Chuang et al. (US 2020/0357955 A1; hereinafter ”Chuang”). Regarding Claim 1, Chuang teaches a semiconductor light emitting device, comprising: a light emitting layer (12, Fig. 3, para [0044] describes an epitaxial stacked layer 12 including a light-emitting layer 36); a first electrode on a lower side of the light emitting layer (16, Fig. 3, para [0042] describes an electrode 16 on a lower side of the light emitting layer 12); a second electrode on an upper side of the light emitting layer (14, Fig. 3, para [0042] describes an electrode 14 on an upper side of the light emitting layer 12); an insulating layer on a side portion of the light emitting layer (18 and 50, Fig. 3, para [0042] describes a reflective stacked layer 18 including at least insulating layers 40 and 44 and a buffer stacked layer including insulating layers 52, 56 and 54 disposed on a side portion of the light emitting layer 12) and overlapping at least a portion of the first electrode and overlapping at least a portion of the second electrode (18, 16 and 14, Fig. 3 depicts wherein the insulating layer 18 overlaps at least a portion of the first electrode 16 and second electrode 14 in a horizontal and vertical direction); and a plurality of metal layers spaced apart from each other in the insulating layer (44 and 60, Fig. 3, para [0047] describes a metal layer 44 and para [0065] describes a metal layer 60 spaced apart from metal layer 44 by an insulating layer 42), the plurality of metal layers including: a first metal layer including a reflective layer (44, Fig. 3, para [0047] describes wherein the first metal layer 44 is a reflective layer); and a second metal layer including a magnetic layer (60, Fig. 3, para [0047] describes wherein the second metal layer 60 may include a magnetic metal material such as nickel). Regarding Claim 2, Chuang teaches the semiconductor light emitting device of claim 1, wherein the light emitting layer comprises: a first conductivity type semiconductor layer (38, Fig. 3, para [0044] describes wherein the light emitting layer 12 includes a second-type semiconductor layer 38, herein the first-type semiconductor layer 38); an active layer on the first conductivity type semiconductor layer (36, Fig. 3, para [0044] describes wherein the light emitting layer 12 includes an active light emitting layer 36 on the first conductivity type semiconductor layer 38); and a second conductivity type semiconductor layer on the active layer (34, Fig. 3, para [0045] describes wherein the light emitting layer 12 includes a first-type semiconductor layer 34, herein the second-type semiconductor layer 34, on the active light emitting layer 36). Regarding Claim 3, Chuang teaches the semiconductor light emitting device of claim 2, wherein the second metal layer is spaced outwardly from the first metal layer (60 and 44, Fig. 3 depicts wherein the second metal layer 60 is spaced outwardly from the first metal layer 44 in a direction outward from the light emitting layer 12). Regarding Claim 4, Chuang teaches the semiconductor light emitting device of claim 3, wherein the insulating layer comprises: a first insulating layer between the light emitting layer and the first metal layer (40, 12 and 44, Fig. 3, para [0047] describes a first insulating layer 40 of the insulating layer 18 wherein the first insulating layer is between the light emitting layer 12 and the first metal layer 44); a second insulating layer between the first metal layer and the second metal layer (42, 44 and 60, Fig. 3, para [0047] describes a second insulating layer 42 of the insulating layer 18 wherein the second insulating layer 42 is between the first metal layer 44 and the second metal layer 60); and a third insulating layer on an outer side surface of the second metal layer (52, Fig. 3, para [0065] describes a third insulating layer 52 of the insulating layer 50 on an outer side surface of the second metal layer 60). Regarding Claim 8, Chuang teaches the semiconductor light emitting device of claim 4, wherein an upper side of at least one of the first metal layer and the second metal layer is located higher than an upper surface of the second conductivity type semiconductor layer (60, 44 and 34, Fig. 3 depicts wherein an upper surface of the first metal layer 44 and second metal layer 60 are both higher than an upper surface of the second conductivity type semiconductor layer 34). Regarding Claim 9, Chuang teaches the semiconductor light emitting device of claim 4, wherein an upper side of at least one of the first metal layer and the second metal layer is in contact with the third insulating layer (60 and 52, Fig. 3 depicts wherein an upper surface of the second metal layer 60 is in contact with the third insulating layer 52). Regarding Claim 11, Chuang teaches the semiconductor light emitting device of claim 4, wherein an upper side of at least one of the first insulating layer and the second insulating layer is in contact with the third insulating layer (42 and 52, Fig. 3 depicts wherein an upper surface of the second insulating layer 42 is in contact with the third insulating layer 52). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tung-Lin Chuang et al. (US 2020/0357955 A1; hereinafter ”Chuang”) in view of Mikio Takiguchi et al. (US 2022/0093833 A1; hereinafter “Takiguchi”). Regarding Claim 7, Chuang discloses all the limitations of Claim 4. Chuang fails to explicitly disclose the semiconductor light emitting device of claim 4, wherein an upper side of at least one of the first metal layer and the second metal layer coincides with an upper surface of the second electrode. However, Takiguchi teaches a similar semiconductor light emitting device, wherein an upper side of at least one of the first metal layer (16B, Fig. 12, para [0074] describes a reflective film 16B formed of a metal material such as copper) and the second metal layer coincides with an upper surface of the second electrode (15 and 16B, Fig. 12, para [0074] describes a second electrode 15 wherein an upper surface of the second electrode 15 and the first metal layer 16B terminate at a same surface 30S1 therefore an upper surface of the first metal layer 16B and an upper surface of the second electrode 15 coincide with each other). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chuang with Takiguchi to further disclose a semiconductor light emitting device wherein an upper side of a first metal layer coincides with an upper surface of a second electrode in order to provide the advantage of providing a planar surface upon which a reflective structure may be mounted onto a light-emitting element thus making it possible to facilitate alignment between the light-emitting element and the reflective structure (Takiguchi, para [0076]) and to further provide the advantage of enabling a second electrode to be installed on a surface of a reflective structure making it possible to further improve light-extraction efficiency and improve the flexibility in disposing a second electrode (Takiguchi, para [0126]). Regarding Claim 19, Chuang discloses all the limitations of Claim 1. Chuang fails to explicitly disclose the semiconductor light emitting device of claim 1, wherein each of the plurality of metal layers has a cylindrical structure. However, Takaguchi teaches a similar semiconductor light emitting device, wherein each of the plurality of metal layers has a cylindrical structure (10 and 16B, Fig. 3B and Fig. 13, para [0089] describes wherein the light-emitting element 10 may have a circular shape as shown in Fig. 3B wherein a metal layer such as reflective layer 16B disposed on a side surface of the circular shape extending in a Y direction as shown in Fig. 1 and Fig. 13 may also have a circular cross section shape resulting in cylindrical metal layers 16B wherein upon combining Chuang with Takaguchi, the resulting structure of Chuang would comprise a plurality of metal layers 44 and 60 having a cylindrical shape). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chuang with Takiguchi to try different shaped structures of metal layers form a finite number of possible shapes of metal layers disposed on a side surface of a light emitting element in order to provide the advantage of enabling metal layers to be conformed to a plurality of possible shapes of light emitting layers in order to meet design requirements for an LED structure requiring a cylindrical structure and to further apply a simple substitution of one known element, such as a trapezoidal shaped LED structure, with another known element, such as a cylindrical shaped LED structure in order to obtain predictable results with a reasonable expectation of success. Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Tung-Lin Chuang et al. (US 2020/0357955 A1; hereinafter ”Chuang”) in view of Changseo Park et al. (US 2018/0240937 A1; hereinafter “Park”). Regarding Claim 20, Chuang teaches a display device, comprising: a semiconductor light emitting device (1B, Fig. 3, para [0065] describes a light emitting diode 1b) including: a light emitting layer (12, Fig. 3, para [0044] describes an epitaxial stacked layer 12 including a light-emitting layer 36); a first electrode on a lower side of the light emitting layer (16, Fig. 3, para [0042] describes an electrode 16 on a lower side of the light emitting layer 12); a second electrode on an upper side of the light emitting layer (14, Fig. 3, para [0042] describes an electrode 14 on an upper side of the light emitting layer 12); an insulating layer on a side portion of the light emitting layer (18 and 50, Fig. 3, para [0042] describes a reflective stacked layer 18 including at least insulating layers 40 and 44 and a buffer stacked layer including insulating layers 52, 56 and 54 disposed on a side portion of the light emitting layer 12), the insulating layer overlapping at least a portion of the first electrode and overlapping at least a portion of the second electrode (18, 16 and 14, Fig. 3 depicts wherein the insulating layer 18 overlaps at least a portion of the first electrode 16 and second electrode 14 in a horizontal and vertical direction); and a plurality of metal layers spaced apart from each other in the insulating layer (44 and 60, Fig. 3, para [0047] describes a metal layer 44 and para [0065] describes a metal layer 60 spaced apart from metal layer 44 by an insulating layer 42), the plurality of metal layers (44 and 60, Fig. 3) including: a first metal layer including a reflective layer (44, Fig. 3, para [0047] describes wherein the first metal layer 44 is a reflective layer); and a second metal layer including a magnetic layer (60, Fig. 3, para [0047] describes wherein the second metal layer 60 may include a magnetic metal material such as nickel); Chuang fails to explicitly disclose a substrate comprising a plurality of sub-pixels constituting a pixel; and a plurality of semiconductor light emitting devices in the plurality of sub-pixels. However, Park describes a similar display device comprising: a substrate (110, Fig. 2, para [0060] describes a substrate 110) comprising a plurality of sub-pixels constituting a pixel (150, Fig. 2, para [0081] describes wherein the substrate 110 comprises a plurality of light-emitting devices 150 constituting a sub-pixel wherein a row of sub-pixels may constitute a pixel); and a plurality of semiconductor light emitting devices in the plurality of sub-pixels (150, Fig. 2, para [0081] describes wherein the each the light-emitting devices 150 constituting a sub-pixel wherein a plurality of light emitting devices 150 are in the plurality of sub-pixels). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chuang with Park to further disclose a display device comprising a plurality of sub-pixels constituting a pixel and a plurality of semiconductor light emitting devices in the plurality of sub-pixels in order to provide the advantage of implementing light-emitting devices in a display device comprising a plurality of sub-pixels of different colors to implement a full-color display (Park, para [0092]). Regarding Claim 21, the combination of Chuang and Park teaches the display device of claim 20, wherein the insulating layer includes: a first insulating layer between the light emitting layer and the first metal layer (Chuang, 40, 12 and 44, Fig. 3, para [0047] describes a first insulating layer 40 of the insulating layer 18 wherein the first insulating layer is between the light emitting layer 12 and the first metal layer 44); a second insulating layer between the first metal layer and the second metal layer (Chuang, 42, 44 and 60, Fig. 3, para [0047] describes a second insulating layer 42 of the insulating layer 18 wherein the second insulating layer 42 is between the first metal layer 44 and the second metal layer 60); and a third insulating layer on an outer side surface of the second metal layer (Chuang, 52, Fig. 3, para [0065] describes a third insulating layer 52 of the insulating layer 50 on an outer side surface of the second metal layer 60). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Feb 27, 2024
Application Filed
Sep 08, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+33.3%)
3y 5m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 7 resolved cases by this examiner. Grant probability derived from career allowance rate.

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