Prosecution Insights
Last updated: October 02, 2026
Application No. 18/589,011

STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE WITH WORD LINE CONTACT VIA STRUCTURES LOCATED OVER SUPPORT FEATURES AND METHODS OF FORMING THE SAME

Non-Final OA §103
Filed
Feb 27, 2024
Examiner
BAIG, ANEESA RIAZ
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
45 granted / 48 resolved
+25.8% vs TC avg
Moderate +8% lift
Without
With
+7.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
15 currently pending
Career history
62
Total Applications
across all art units

Statute-Specific Performance

§103
47.9%
+7.9% vs TC avg
§102
24.7%
-15.3% vs TC avg
§112
26.3%
-13.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 48 resolved cases

Office Action

§103
Attorney’s Docket Number: 3590-1277A Filing Date: 02/27/2024 Claimed Priority Date: N/A Applicants: Kubo et al. Examiner: Aneesa Baig DETAILED ACTION This Office action responds to the election filed on 06/11/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s elections without traverse of Group II Invention, directed to a memory device, and of Species I (reading on Figs. 1-11) in the reply filed on 06/11/2026, is acknowledged. Applicant indicated that claims 1-14 read on the elected Group I, Species I. The examiner agrees. Accordingly, claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species. 2 Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Kubo et al. (US Pub. 20220328413, Hereinafter Kubo) in view of Lee et al Lee et al (US. Pub. 20220310515, Hereinafter Lee) Regarding Claim 1, Kubo (e.g., Fig. 69C and 70, [122][154], [156], [318]-[319]) shows a 3D memory comprising: an alternating stack of insulating layers (132, 232, 270) and electrically conductive layers (146, 246), wherein the electrically conductive layers comprise a first electrically conductive layer, second electrically conductive layers that overlie the first electrically conductive layer, and third electrically conductive layers that underlie the first electrically conductive layer (146 layers, see image below); a memory opening vertically extending through the alternating stack (49, Fig. 16D, Fig 69C, [307]); a memory opening fill structure located in memory opening and comprising a vertical stack of memory elements (50,55) located at levels of the electrically conductive layers and a vertical semiconductor channel (60L) (Fig 16D [163]-[169]); and a layer contact assembly comprising a layer contact via structure (86) vertically extending through each layer within the alternating stack and laterally contacting a cylindrical surface of the first electrically conductive layer, and further comprising (the first electrically conductive layer contacts the surface of the via 86 [0139]) While Kubo shows a contact via structure, it is silent regarding the first annular insulating fins laterally surrounding the layer contact via structure and located at each level of the second electrically conductive layers, Lee (Fig 11A, 12, [0200]-[0205]), on the other hand and in a related field of contact via structures, teaches a 3D memory device having gate contact plugs (289) that include protrusions (289E) protruding in a horizontal direction to contact the gate pads. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the layer contact via structure of Kubo to include horizontal protrusions as taught by Lee. A person of ordinary skill in the art would have been motivated to make this modification to increase the contact area between the contact plug and the conductive layer, reducing contact resistance and improving device reliability. PNG media_image1.png 521 708 media_image1.png Greyscale Allowable Subject Matter Claims 2-14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANEESA RIAZ BAIG/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Feb 27, 2024
Application Filed
Sep 21, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
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FINE BUMP PITCH DIE TO DIE TILING INCORPORATING AN INVERTED GLASS INTERPOSER
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Patent 12720932
LIGHT-EMITTING DIODE DEVICES WITH SUPPORT STRUCTURES INCLUDING PATTERNED LIGHT-ALTERING LAYERS
3y 8m to grant Granted Aug 25, 2026
Patent 12713978
LIGHT-EMITTING DIODE DEVICES WITH SUPPORT ELEMENTS FOR IMPROVED NEAR-FIELD AND FAR-FIELD EMISSIONS
3y 9m to grant Granted Aug 18, 2026
Patent 12713960
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 6m to grant Granted Aug 18, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
99%
With Interview (+7.9%)
3y 4m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 48 resolved cases by this examiner. Grant probability derived from career allowance rate.

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